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LPC61W492 advance information integrated super i/o controller for lpc bus with game and midi ports/plus hardware monitoring functions features !" 5 volt operation !" lpc bus interface !" supports nldrq (lpc dma), serirq (serial irq) !" pc 98/99 and acpi 1.0 compliant !" supports dpm (device power management), acpi !" programmable configuration settings !" single 24 or 48 mhz clock input !" floppy disk controller (fdc) - compatible with ibm pc/at disk drive systems - variable write pre-compensation with track selectable capability - supports vertical recording format - dma enable logic - 16-byte data fifos - supports floppy disk drives and tape drives - detects all overrun and underrun conditions - built-in address mark detection circuit to simplify the read electronics - fdd anti-virus functions with software write protect and fdd write enable signal (write data signal was forced to be inactive) - supports up to four 3.5-inch or 5.25- inch floppy disk drives - completely compatible with industry standard 82077 - 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2mbps data transfer rate - supports 3-mode fdd, and its win95/98 driver !" uart - two high-speed 16550 compatible uarts with 16-byte send/receive fifos - midi compatible - fully programmable serial-interface characteristics: - 5, 6, 7 or 8-bit characters - even, odd or no parity bit generation/detection - 1, 1.5 or 2 stop bits generation - internal diagnostic capabilities: - loop-back controls for communications link fault isolation - break, parity, overrun, framing error simulation - programmable baud generator allows division of 1.8461 mhz and 24 mhz by 1 to (216-1) - maximum baud rate up to 921 kbps for 14.769 mhz and 1.5 mbps for 24 mhz ordering information order number: LPC61W492qfp 128 pin qfp package
2 !" infrared - supports irda version 1.0 sir protocol with maximum baud rate up to 115.2 kbps - supports sharp ask ir protocol with maximum baud rate up to 57,600 bps - supports consumer ir !" parallel port - compatible with ibm parallel port - supports ps/2 compatible bidirectional parallel port - supports enhanced parallel port (epp) ! compatible with ieee 1284 specification - supports extended capabilities port (ecp) ! compatible with ieee 1284 specification - extension fdd mode supports disk drive b; and extension 2fdd mode supports disk drives a and b through parallel port - enhanced printer port back-drive current protection !" keyboard controller - 8042 based with optional f/w from amikkeytm-2 - asynchronous access to two data registers and one status register - software compatibility with the 8042 - supports ps/2 mouse - supports port 92 - supports both interrupt and polling modes - fast gate a20 and hardware keyboard reset - 8 bit timer/counter - supports binary and bcd arithmetic - 6 mhz, 8 mhz, 12 mhz, or 16 mhz operating frequency !" game port - supports two separate joysticks - supports every joystick two axis (x,y) and two button (a,b) controllers !" midi port - baud rate is 31.25 kbaud - 16-byte input fifo - 16-byte output fifo !" general purpose i/o ports - 22 programmable general purpose i/o ports - general purpose i/o ports can serve as simple i/o ports, interrupt steering inputs, watch dog timer output, power led output, infrared i/o pins, kbc control i/o pins, suspend led output, nrsmrst signal, pwrok signal, beep output - functional in power down mode (gp1 only) !" onnow functions - keyboard wake-up by programmable keys - mouse wake-up by programmable buttons - cir wake-up by programmable keys - on now wake-up from all of the acpi sleeping states (s1-s5) !" hardware monitor functions - five vid input pins for cpu vcore identification - three thermal inputs from optionally remote thermistors or 2n3904 transistors or pentium ? ii thermal diode output - seven positive voltage inputs (typical for +12v, -12v, +5v, -5v, +3.3v, vcorea, vcoreb) - two intrinsic voltage monitoring (typical for vbat, +5vsb) - three fan speed monitoring inputs - two fan speed controls - built in case open detection circuit - watchdog comparison of all monitored values - programmable hysteresis and setting points for all monitored items - over temperature indicate output - automatic power on voltage detection beep
3 - issue nsmi, irq, novt to activate system protection - intel ldcmtm/acer admtm compatible general description the LPC61W492 is an evolving product from smsc's most popular i/o family. it features a whole new interface, namely lpc ( low pin count ) interface, which will be supported in the next generation intel chip-set. this interface as its name suggests is to provide an economical implementation of i/o's interface with lower pin count and still maintains equivalent performance as its isa interface counterpart. approximately 40 pin counts are saved in lpc i/o comparing to isa implementation. with this additional freedom, we can implement more devices on a single chip as demonstrated in LPC61W492's integration of game port and midi port. it is fully transparent in terms of software which means no bios or device driver update is needed except chip-specific configuration. the disk drive adapter functions of LPC61W492 include a floppy disk drive controller compatible with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and dma logic. the wide range of functions integrated onto the LPC61W492 greatly reduces the number of components required for interfacing with floppy disk drives. the LPC61W492 supports four 360k, 720k, 1.2m, 1.44m, or 2.88m disk drives and data transfer rates of 250 kb/s, 300 kb/s, 500 kb/s, 1 mb/s, and 2 mb/s. the LPC61W492 provides two high-speed serial communication ports (uarts), one of which supports serial infrared communication. each uart includes a 16-byte send/receive fifo, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. both uarts provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k , 460k , or 921kbps which support higher speed modems. in addition, the LPC61W492 provides ir functions: irda 1.0 ( sir for 1.152k bps) and tv remote ir ( consumer ir , supporting nec, rc-5, extended rc-5, and recs-80 protocols). the LPC61W492 supports one pc-compatible printer port (spp), bi-directional printer port (bpp) and also enhanced parallel port (epp) and extended capabilities port (ecp). through the printer port interface pins, also available are: extension fdd mode and extension 2fdd mode allowing one or two external floppy disk drives to be connected. the configuration registers support mode selection, function enable/disable, and power down function selection. furthermore, the configurable pnp features are compatible with the plug-and-play feature demand of windows 95/98?, which makes system resource allocation more efficient than ever. the LPC61W492 provides functions that complies with acpi ( advanced configuration and power interface ), which includes support of legacy and acpi power management through npme or npsout function pins. for onnow keyboard wake-up, onnow mouse wake-up, and onnow cir wake-up. the LPC61W492 also has auto power management to reduce the power consumption. the keyboard controller is based on 8042 compatible instruction set with a 2k byte programmable rom and a 256-byte ram bank. keyboard bios firmware are available with
4 optional amikey -2, phoenix multikey/42, or customer code. the LPC61W492 provides a set of flexible i/o control functions to the system designer through a set of general purpose i/o ports. these gpio ports may serve as simple i/o or may be individually configured to provide a predefined alternate function. general purpose port 1 is designed to be functional even in power down mode (vcc is off). the LPC61W492 is made to fully comply with microsoft pc98 and pc99 hardware design guide . moreover LPC61W492 is made to meet the specification of pc98/pc99's requirement in the power management: acpi and dpm (device power management). the LPC61W492 contains a game port and a midi port. the game port is designed to support 2 joysticks and can be applied to all standard pc game control devices, they are very important for an entertainment or consumer computer. only the LPC61W492 supports hardware status monitoring for personal computers. it can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly.
5 table of contents features ............................................................................................................................... ........... 1 general description ................................................................................................................ 3 LPC61W492 pin configuration .............................................................................................. 8 pin description ........................................................................................................................... 9 lpc i nterface ............................................................................................................................... ..9 fdc i nterface ............................................................................................................................... 10 m ulti -m ode p arallel p ort .........................................................................................................11 s erial p ort i nterface .................................................................................................................16 kbc i nterface ............................................................................................................................... 17 acpi i nterface ..............................................................................................................................1 7 h ardware m onitor i nterface ...................................................................................................17 g ame p ort & midi p ort ..............................................................................................................18 g eneral p urpose i/o p ort .........................................................................................................19 power pins ............................................................................................................................... ..20 lpc (low pin count) interface .......................................................................................... 21 fdc functional description .............................................................................................. 22 LPC61W492 fdc ..........................................................................................................................22 r egister d escriptions ................................................................................................................34 uart port ............................................................................................................................... ....... 45 u niversal a synchronous r eceiver /t ransmitter (uart a, uart b) ..............................45 r egister a ddress ........................................................................................................................45 cir receiver port ..................................................................................................................... 53 cir r egisters ............................................................................................................................... 53 parallel port ............................................................................................................................ 60 p rinter i nterface l ogic .............................................................................................................60 e nhanced p arallel p ort (epp) .................................................................................................61 e xtended c apabilities p arallel (ecp) p ort ..........................................................................66 e xtension fdd m ode (extfdd) ...............................................................................................74 e xtension 2fdd m ode (ext2fdd) ...........................................................................................74 keyboard controller .......................................................................................................... 75 o utput b uffer ..............................................................................................................................7 6
6 i nput b uffer ............................................................................................................................... ...76 s tatus r egister ...........................................................................................................................76 c ommands ............................................................................................................................... ........77 hardware gatea20/keyboard reset control logic .........................................79 general purpose i/o ............................................................................................................... 80 plug and play configuration ........................................................................................... 82 c ompatible p n p .............................................................................................................................82 c onfiguration s equence ............................................................................................................83 acpi registers features ...................................................................................................... 85 hardware monitor .................................................................................................................. 86 g eneral d escription ...................................................................................................................86 a ccess i nterface .........................................................................................................................86 a nalog i nputs ............................................................................................................................... .92 fan s peed c ount and fan s peed c ontrol ...........................................................................95 n smi i nterrupt m ode ..................................................................................................................98 n ovt i nterrupt m ode ...............................................................................................................101 registers and ram ..............................................................................................................102 serial irq ............................................................................................................................... ...... 134 s tart f rame ............................................................................................................................... ..134 irq/d ata f rame ..........................................................................................................................134 s top f rame ............................................................................................................................... ...135 configuration register .................................................................................................... 136 c hip (g lobal ) c ontrol r egister ............................................................................................136 l ogical d evice 0 (fdc) .............................................................................................................140 l ogical d evice 1 (p arallel p ort ) ...........................................................................................142 l ogical d evice 2 (uart a)) ....................................................................................................143 l ogical d evice 3 (uart b) .......................................................................................................143 l ogical d evice 5 (kbc) ..............................................................................................................145 l ogical d evice 6 (cir) ...............................................................................................................145 l ogical d evice 7 (g ame p ort and midi p ort and gpio p ort 1) .....................................146 l ogical d evice 8 (gpio p ort 2) ..............................................................................................146 l ogical d evice 9 (gpio p ort 3 t his power of the p ort is standby source (vsb) ) ..147 l ogical d evice a (acpi) ............................................................................................................148 l ogical d evice b (h ardware m onitor ) .................................................................................153 specifications .......................................................................................................................... 154 a bsolute m aximum r atings ......................................................................................................154
7 dc characteristics ............................................................................................................154 application circuits ............................................................................................................. 157 p arallel p ort e xtension fdd ................................................................................................157 p arallel p ort e xtension 2fdd ..............................................................................................158 f our fdd m ode ..........................................................................................................................158 package dimensions ............................................................................................................. 159
8 LPC61W492 pin configuration lpc61w49x 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 vtin2 vtin1 novt vid4 vid3 vid2 vid1 vid0 fanio3 fanio2 fanio1 vcc fanpwm2 fanpwm1 vss beep msi/gp20 mso/irqin0 gpsa2/gp17 gpsb2/gp16 gpy1/gp15 gpy2/p16/gp14 gpx2/p15/gp13 gpx1/p14/gp12 gpsb1/p13/gp11 gpsa1/p12/gp10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 drvden0 d rvden1/irqin1/gp27 nindex nmoa ndsb ndsa nmob ndir nstep nwd nwe vcc ntrak0 nwp nrdata nhead ndskchg clkin npme vss pciclk nldrq serirq lad3 lad2 lad1 lad0 vcc3v nlframe nlreset slct pe busy nack pd7 pd6 pd5 pd4 susled/gp3 5 kdat kclk vsb kbrst ga20m nkblock nria ndcda vss souta sina ndtra nrtsa ndsra nctsa vcc nstb nafd nerr ninit nslin pd0 pd1 pd2 pd3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 vtin3 vref vcorea vcoreb +3.3vin avcc +12vin -12vin -5vin agnd scl/gp21 sda/gp22 pled/gp23 wdto/gp24 irrx/gp25 irtx/gp26 vss nrib ndcdb soutb sinb ndtrb nrtsb ndsrb nctsb vcc ncaseopen susclkin vbat nslp_sx/gp30 npwrctl/gp31 pwrok/gp32 nrsmrst/gp33 cirrx/gp34 psin npsout mdat mclk 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 LPC61W492
9 pin description note: please refer to section 13.2 dc characteristics for details. i/o 8t ttl level bi-directional pin with 8 ma source-sink capability i/o 12t ttl level bi-directional pin with 12 ma source-sink capability i/o 12tp3 3.3v ttl level bi-directional pin with 12 ma source-sink capability i/od 12t ttl level bi-directional pin open drain output with 12 ma sink capability i/o 24t ttl level bi-directional pin with 24 ma source-sink capability out 12t ttl level output pin with 12 ma source-sink capability out 12tp3 3.3v ttl level output pin with 12 ma source-sink capability od 12 open-drain output pin with 12 ma sink capability od 24 open-drain output pin with 24 ma sink capability in cs cmos level schmitt-trigger input pin in t ttl level input pin in td ttl level input pin with internal pull down resistor in ts ttl level schmitt-trigger input pin in tsp3 3.3v ttl level schmitt-trigger input pin lpc interface symbol pin i/o function clkin 18 in t system clock input. according to the input frequency 24mhz or 48mhz, it is selectable through register. default is 24mhz input. npme 19 od 12 generated pme event. pciclk 21 in tp3 pci clock input. nldrq 22 o 12tp3 encoded dma request signal. serirq 23 i/od 2tp3 serial irq input/output. lad[3:0] 24-27 i/o 12tp3 these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. nlframe 29 in tsp3 indicates start of a new cycle or termination of a broken cycle. nlreset 30 in tsp3 reset signal. it can be connected to npcirst signal on the host. susclkin 75 ints 32khz clock input, for cir only.
10 fdc interface symbol pin i/o function drvden0 1 od 24 drive density select bit 0. drvden1 2 od 12 drive density select bit 1. irqin1 gp27 in i/od 12 alternate function input: interrupt channel input. general purpose i/o port 3 bit 6. nindex 3 in cs this schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. this input pin is pulled up internally by a 1 k " resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). nmoa 4 od 24 motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. ndsb 5 od 24 drive select b. when set to 0, this pin enables disk drive b. this is an open drain output. ndsa 6 od 24 drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. nmob 7 od 24 motor b on. when set to 0, this pin enables disk drive 1. this is an open drain output. ndir 8 od 24 direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion nstep 9 od 24 step output pulses. this active low open drain output produces a pulse to move the head to another track. nwd 10 od 24 write data. this logic low open drain writes pre- compensation serial data to the selected fdd. an open drain output. nwe 11 od 24 write enable. an open drain output. ntrak0 13 in cs track 0. this schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. this input pin is pulled up internally by a 1 k " resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). nwp 14 in cs write protected. this active low schmitt input from the disk drive indicates that the diskette is write-protected. this input pin is pulled up internally by a 1 k " resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). nrdata 15 in cs the read data input signal from the fdd. this input pin is pulled up internally by a 1 k " resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn).
11 fdc interface, continued symbol pin i/o function nhead 16 od 24 head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 ndskchg 17 in cs diskette change. this signal is active low at power on and whenever the diskette is removed. this input pin is pulled up internally by a 1 k "# resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). multi-mode parallel port the following pins have alternate functions, which are controlled by cr28 and l3-crf0. symbol pin i/o function slct 31 in t printer mode: an active high input on this pin indicates that the printer is selected. this pin is pulled high internally. refer to the description of the parallel port for definition of this pin in ecp and epp mode. od 12 extension fdd mode: nwe2 this pin is for extension fdd b; its function is the same as the nwe pin of fdc. od 12 extension 2fdd mode: nwe2 this pin is for extension fdd a and b; its function is the same as the nwe pin of fdc. pe 32 in t printer mode: an active high input on this pin indicates that the printer has detected the end of the paper. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. od 12 extension fdd mode: nwd2 this pin is for extension fdd b; its function is the same as the nwd pin of fdc. od 12 extension 2fdd mode: nwd2 this pin is for extension fdd a and b; its function is the same as the nwd pin of fdc.
12 multi-mode parallel port, continued symbol pin i/o function busy 33 in t printer mode: an active high input indicates that the printer is not ready to receive data. this pin is pulled high internally. refer to the description of the parallel port for definition of this pin in ecp and epp mode. od 12 extension fdd mode: nmob2 this pin is for extension fdd b; its function is the same as the nmob pin of fdc. od 12 extension 2fdd mode: nmob2 this pin is for extension fdd a and b; its function is the same as the nmob pin of fdc. nack 34 in t od 12 od 12 printer mode: nack an active low input on this pin indicates that the printer has received data and is ready to accept more data. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ndsb2 this pin is for the extension fdd b; its functions is the same as the ndsb pin of fdc. extension 2fdd mode: ndsb2 this pin is for extension fdd a and b; its function is the same as the ndsb pin of fdc. nerr 45 in t od 12 od 12 printer mode: nerr an active low input on this pin indicates that the printer has encountered an error condition. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nhead2 this pin is for extension fdd b; its function is the same as the nheadpin of fdc. extension 2fdd mode: nhead2 this pin is for extension fdd a and b; its function is the same as the nhead pin of fdc.
13 multi-mode parallel port, continued symbol pin i/o function nslin 43 od 12 od 12 od 12 printer mode: nslin output line for detection of printer selection. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nstep2 this pin is for extension fdd b; its function is the same as the nstep pin of fdc. extension 2fdd mode: nstep2 this pin is for extension fdd a and b; its function is the same as the nstep pin of fdc. ninit 44 od 12 od 12 od 12 printer mode: ninit output line for the printer initialization. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ndir2 this pin is for extension fdd b; its function is the same as the ndir pin of fdc. extension 2fdd mode: ndir2 this pin is for extension fdd a and b; its function is the same as the ndir pin of fdc. nafd 46 od 12 od 12 od 12 printer mode: nafd an active low output from this pin causes the printer to auto feed a line after a line is printed. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: drvden0 this pin is for extension fdd b; its function is the same as the drvden0 pin of fdc. extension 2fdd mode: drvden0 this pin is for extension fdd a and b; its function is the same as the drvden0 pin of fdc.
14 multi-mode parallel port, continued symbol pin i/o function nstb 47 od 12 printer mode: nstb an active low output is used to latch the parallel data into the printer. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. - extension fdd mode: this pin is a tri-state output. - extension 2fdd mode: this pin is a tri-state output. pd0 42 i/o 14t printer mode: pd0 parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. in t extension fdd mode: nindex2 this pin is for extension fdd b; its function is the same as the nindex pin of fdc. it is pulled high internally. in t extension 2fdd mode: nindex2 this pin is for extension fdd a and b; its function is the same as the nindex pin of fdc. it is pulled high internally. pd1 41 i/o 14t in t in t printer mode: pd1 parallel port data bus bit 1. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ntrak02 this pin is for extension fdd b; its function is the same as the ntrak0 pin of fdc. it is pulled high internally. extension. 2fdd mode: ntrak02 this pin is for extension fdd a and b; its function is the same as the ntrak0 pin of fdc. it is pulled high internally. pd2 40 i/o 14t in t in t printer mode: pd2 parallel port data bus bit 2. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nwp2 this pin is for extension fdd b; its function is the same as the nwp pin of fdc. it is pulled high internally. extension. 2fdd mode: nwp2 this pin is for extension fdd a and b; its function is the same as the nwp pin of fdc. it is pulled high internally.
15 multi-mode parallel port, continued symbol pin i/o function pd3 39 i/o 14t in t in t printer mode: pd3 parallel port data bus bit 3. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nrdata2 this pin is for extension fdd b; its function is the same as the nrdata pin of fdc. it is pulled high internally. extension 2fdd mode: nrdata2 this pin is for extension fdd a and b; its function is the same as the nrdata pin of fdc. it is pulled high internally. pd4 38 i/o 14t in t in t printer mode: pd4 parallel port data bus bit 4. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ndskchg2 this pin is for extension fdd b; the function of this pin is the same as the ndskchg pin of fdc. it is pulled high internally. extension 2fdd mode: ndskchg2 this pin is for extension fdd a and b; this function of this pin is the same as the ndskchg pin of fdc. it is pulled high internally. pd5 37 i/o 14t - - printer mode: pd5 parallel port data bus bit 5. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension 2fdd mode: this pin is a tri-state output. pd6 36 i/od 14t - od 14 printer mode: pd6 parallel port data bus bit 6. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension. 2fdd mode: nmoa2 this pin is for extension fdd a; its function is the same as the nmoa pin of fdc. pd7 35 i/od 14t - od 14 printer mode: pd7 parallel port data bus bit 7. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension 2fdd mode: ndsa2 this pin is for extension fdd a; its function is the same as the ndsa pin of fdc.
16 serial port interface symbol pin i/o function nctsa nctsb 49 78 in t clear to send. it is the modem control input. the function of these pins can be tested by reading bit 4 of the handshake status register. ndsra ndsrb 50 79 in t data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. nrtsa 51 i/o 8t uart a request to send. an active low signal informs the modem or data set that the controller is ready to send data. hefras during power-on reset, this pin is pulled down internally and is defined as hefras, which provides the power-on value for cr26 bit 6 (hefras). a 4.7 k " is recommended if intends to pull up. (select 370h as configuration i/o port $ s address) nrtsb 80 i/o 8t uart b request to send. an active low signal informs the modem or data set that the controller is ready to send data. ndtra npnpcsv 52 i/o 8t uart a data terminal ready. an active low signal informs the modem or data set that the controller is ready to communicate. during power-on reset, this pin is pulled down internally and is defined as npnpcsv, which provides the power-on value for cr24 bit 0 (npnpcsv). a 4.7 k " is recommended if intends to pull up. (clear the default value of fdc, uarts, and prt) ndtrb 81 i/o 8t uart b data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. sina sinb 53 82 in t serial input. it is used to receive serial data through the communication link. souta 54 i/o 8t uart a serial output. it is used to transmit serial data out to the communication link. penkbc during power-on reset, this pin is pulled down internally and is defined as penkbc, which provides the power-on value for cr24 bit 2 (enkbc). a 4.7 k " resistor is recommended if intends to pull up. (enable kbc) soutb pen48 83 i/o 8t uart b serial output. during power-on reset, this pin is pulled down internally and is defined as pen48, which provides the power-on value for cr24 bit 6 (en48). a 4.7 k " resistor is recommended if intends to pull up. ndcda ndcdb 56 84 in t data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. nria nrib 57 85 in t ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set.
17 kbc interface symbol pin i/o function nkblock 58 int keyboard inhibit control input. this pin is after system reset. internal pull high. (kbc p17) ga20m 59 o12 gate a20 output. this pin is high after system reset. (kbc p21) kbrst 60 o12 keyboard reset. this pin is high after system reset. (kbc p20) kdata 63 i/od 16 keyboard data. mdata 66 i/od 16 ps2 mouse data. kclk 62 i/od 16 keyboard clock. mclk 65 i/od 16 ps2 mouse clock. acpi interface symbol pin i/o function vbat 74 pwr battery voltage input. npsout 67 od 12 panel switch output. this signal is used for wake-up system from s5 cold state. this pin is pulse output, active low. npsin 68 in td panel switch input. this pin is high active with an internal pull down resistor. hardware monitor interface symbol pin i/o function ncaseopen 76 in t case open. an active low input from an external device when case is opened. this signal can be latched if pin vbat is connect to battery, even LPC61W492 is power off. -5vin 94 ain 0v to 4.096v fsr analog inputs. -12vin 95 ain 0v to 4.096v fsr analog inputs. +12vin 96 ain 0v to 4.096v fsr analog inputs. +3.3vin 98 ain 0v to 4.096v fsr analog inputs. vcoreb 99 ain 0v to 4.096v fsr analog inputs. vcorea 100 ain 0v to 4.096v fsr analog inputs. vref 101 aout reference voltage for temperature measuring. vtin3 102 ain temperature sensor 3 input. it is used for cpu2 temperature measuring. vtin2 103 ain temperature sensor 2 input. it is used for cpu1 temperature measuring. vtin1 104 ain temperature sensor 1 input. it is used for system temperature measuring. novt 105 od 12 over temperature shutdown output. it indicated the vtin2 or vtin3 is over temperature limit. vid[4:0] 106- 110 in t voltage supply readouts from pentium ii .
18 symbol pin i/o function fanio[3:1] 111- 113 i/o 12ts 0v to +5v amplitude fan tachometer input. alternate function: fan on-off control output. these multifunctional pins can be programmable input or output. fanpwm1 fanpwm2 116 115 o 12 fan speed control. use the pulse width modulation ( pwm ) technical knowledge to control the fan's rpm. beep 118 od12 beep function for hardware monitor. this pin is low after system reset. game port & midi port symbol pin i/o function gpsa1 gp10 128 in i/od 12 active-low, joystick i switch input 1. this pin has an internal pull-up resistor. (default) general purpose i/o port 1 bit 0. p12 i/od24 alternate function output:kbc p12 i/o port. gpsb1 gp11 127 in i/od 12 active-low, joystick ii switch input 1. this pin has an internal pull-up resistor. (default) general purpose i/o port 1 bit 1. p13 i/od12 alternate function output:kbc p13 i/o port. gpx1 gp12 126 i/od i/od 12 joystick i timer pin. this pin connect to x positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 2. p14 i/od12 alternate function output:kbc p14 i/o port. gpx2 gp13 125 i/od i/od 12 joystick ii timer pin. connect this pin to x positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 3. p15 i/od12 alternate function output:kbc p15 i/o port. gpy2 gp14 124 i/od i/od 12 joystick ii timer pin. connect this pin to y positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 4. p16 i/od12 alternate function output:kbc p16 i/o port. gpy1 123 i/od joystick i timer pin. connect this pin to y positioning variable resistors for the joystick. (default) gp15 i/od12 general purpose i/o port 1 bit 5. gpsb2 122 in active-low, joystick ii switch input 2. this pin has an internal pull-up resistor. (default) gp16 i/od 24 general purpose i/o port 1 bit 6. gpsa2 121 in active-low, joystick i switch input 2. this pin has an internal pull-up resistor. (default) gp17 i/od 12 general purpose i/o port 1 bit 7. msi gp20 119 int i/od 12t midi serial data input. schmitt trigger input with internal pull- up register. (default) general purpose i/o port 2 bit 0. mso irqin0 120 ot int midi serial data output. (default) alternate function input: interrupt channel input.
19 general purpose i/o port general purpose i/o port 1 (power source is vcc) general purpose i/o port 2 (power source is vcc) symbol pin i/o function gp20 msi 119 i/od 12t int general purpose i/o port 2 bit 0. midi serial data input. schmitt trigger input with internal pull-up register. (default) gp21 (scl) 92 i/od 12t ints general purpose i/o port 2 bit 1. (alternate function: serial bus clock. for LPC61W492 only) gp22 (sda) 91 i/od 12t i/od12ts general purpose i/o port 2 bit 2. (alternate function: serial bus bi-directional data. for LPC61W492 only) gp23 pled 90 i/od 24t od24t general purpose i/o port 2 bit 3. alternate function output: (default) power led output, this signal is low after system reset. gp24 89 i/od 12t general purpose i/o port 2 bit 4. (default) wdto od 12t alternate function : watch dog timer output. gp25 irrx 88 i/od 24t ints general purpose i/o port 2 bit 5. alternate function input: infrared receiver input. gp26 irtx 87 i/od 24t out12t general purpose i/o port 2 bit 6. alternate function output: infrared transmitter output. gp27 drvden1 irqin1 2 i/od 24t od24t int general purpose i/o port 2 bit 7. drive density select bit 0. alternate function input: interrupt channel input.
20 general purpose i/o port 3 (power source is vsb) symbol pin i/o function gp30 73 i/od12t general purpose i/o port 3 bit 0. nslp_sx int chipset suspend c status input. gp31 72 i/od 12t general purpose i/o port 3 bit 1. npwrctl od 12t alternate function output: (default) this pin generates the pwrctl# signal while the power failure. gp32 71 i/od 12t general purpose i/o port 3 bit 2. pwrok od 12t alternate function output: (default) this pin generates the pwrok signal while the vcc come in. gp33 70 i/od 12t general purpose i/o port 3 bit 3. nrsmrst od 12t alternate function output: (default) this pin generates the rsmrst signal while the vsb come in. gp34 69 i/od 12t general purpose i/o port 3 bit 4. ncirrx od 12t alternate function input: (default) consumer ir receiving input. this pin can wake-up system from s5 cold. gp35 64 i/od 24t general purpose i/o port 3 bit 5. susled od 24t alternate function output : (default) suspend led output, it can program to flash when suspend state. this function can work without vcc. power pins symbol pin function vcc 12, 48, 77, 114 +5v power supply for the digital circuitry. vsb 61 +5v stand-by power supply for the digital circuitry. vcc3v 28 +3.3v power supply for driving 3v on host interface. avcc 97 analog vcc input. internally supplier to all analog circuitry. agnd 93 internally connected to all analog circuitry. the ground reference for all analog inputs.. vss 20, 55, 86, 117 ground.
21 lpc (low pin count) interface lpc interface is to replace isa interface serving as a bus interface between host (chip-set) and peripheral (smsc i/o). data transfer on the lpc bus are serialized over a 4 bit bus. the general characteristics of the interface implemented in smsc lpc i/o are: %# one control line, namely nlframe, which is used by the host to start or stop transfers. no peripherals drive this signal. %# the lad[3:0] bus, which communicates information serially. the information conveyed are cycle type, cycle direction, chip selection, address, data, and wait states. %# mr (master reset) of smsc isa i/o is replaced with an active low reset signal, namely nlreset, in smsc lpc i/o. %# an additional 33 mhz pci clock is needed in smsc lpc i/o for synchronization. %# dma requests are issued through nldrq. %# interrupt requests are issued through serirq. %# power management events are issued through npme. comparing to its isa counterpart, lpc implementation saves up to 40 pins (see table below) which are free for integrating more devices on a single chip. smsc i/o interface pins count fdc37m72x d[7:0], sa[15:0], drq[3:0], dnack[3:0], tc, nior, niow, iochrdy, irqs 49 LPC61W492 lad[3:0], nlframe, pciclk, nldrq, serirq, npme 9 save 40 the transition from isa to lpc is transparent in terms of software which means no bios or device driver update is needed except chip-specific configuration.
22 fdc functional description LPC61W492 fdc the floppy disk controller of the LPC61W492 integrates all of the logic required for floppy disk control. the fdc implements a pc/at or ps/2 solution. all programmable options default to compatible values. the fifo provides better system performance in multi-master systems. the digital data separator supports up to 2 m bits/sec data rate. the fdc includes the following blocks: at interface, precompensation, data rate selection, digital data separator, fifo, and fdc core. at interface the interface consists of the standard asynchronous signals: nrd, nwr, a0-a3, irq, dma control, and a data bus. the address lines select between the configuration registers, the fifo and control/status registers. this interface can be switched between pc/at, model 30, or ps/2 normal modes. the ps/2 register sets are a superset of the registers found in a pc/at. fifo (data) the fifo is 16 bytes in size and has programmable threshold values. all command parameter information and disk data transfers go through the fifo. data transfers are governed by the rqm and dio bits in the main status register. the fifo defaults to disabled mode after any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command. the advantage of the fifo is that it allows the system a larger dma latency without causing disk errors. the following tables give several examples of the delays with a fifo. the data are based upon the following formula: threshold # & (1/data/rate) *8 - 1.5 ' s = delay fifo threshold maximum delay to servicing at 500kbps data rate 1 byte 1 & 16 ' s - 1.5 ' s = 14.5 ' s 2 byte 2 & 16 ' s - 1.5 ' s = 30.5 ' s 8 byte 8 & 16 ' s - 1.5 ' s = 6.5 ' s 15 byte 15 & 16 ' s - 1.5 ' s = 238.5 ' s fifo threshold maximum delay to servicing at 1mbps data rate 1 byte 1 & 8 ' s - 1.5 ' s = 6.5 ' s 2 byte 2 & 8 ' s - 1.5 ' s = 14.5 ' s 8 byte 8 & 8 ' s - 1.5 ' s = 62.5 ' s 15 byte 15 & 8 ' s - 1.5 ' s = 118.5 ' s at the start of a command the fifo is always disabled and command parameters must be sent based upon the rqm and dio bit settings in the main status register. when the fdc enters the command execution phase, it clears the fifo of any data to ensure that invalid data are not transferred. an overrun and underrun will terminate the current command and the data transfer. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered.
23 dma transfers are enabled with the specify command and are initiated by the fdc by activating the drq pin during a data transfer command. the fifo is enabled directly by asserting dnack and addresses need not be valid. note that if the dma controller is programmed to function in verify mode a pseudo read is performed by the fdc based only on dnack. this mode is only available when the fdc has been configured into byte mode (fifo disabled) and is programmed to do a read. with the fifo enabled the above operation is performed by using the new verify command. no dma operation is needed. data separator the function of the data separator is to lock onto the incoming serial read data. when a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. the synchronized clock, called the data window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. serial to parallel conversion logic separates the read data into clock and data bytes. the digital data separator (dds) has three parts: control logic, error adjustment, and speed tracking. the dds circuit cycles once every 12 clock cycles ideally. any data pulse input will be synchronized and then adjusted by immediate error adjustment. the control logic will generate rdd and rwd for every pulse input. during any cycle where no data pulse is present, the dds cycles are based on speed. a digital integrator is used to keep track of the speed changes in the input data stream. write precompensation the write precompensation logic is used to minimize bit shifts in the rddata stream from the disk drive. shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. the fdc monitors the bit stream that is being sent to the drive. the data patterns that require precompensation are well known. depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. perpendicular recording mode the fdc is also capable of interfacing directly to perpendicular recording floppy drives. perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. this scheme packs more data bits into the same area. fdcs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. a single command puts the fdc into perpendicular mode. all other commands operate as they normally do. the perpendicular mode requires a 1 mbps data rate for the fdc. at this data rate the fifo eases the host interface bottleneck due to the speed of data transfer to or from the disk. fdc core the LPC61W492 fdc is capable of performing twenty commands. each command is initiated by a multi-byte transfer from the microprocessor. the result can also be a multi-byte transfer back to the microprocessor. each command consists of three phases: command, execution, and result.
24 command the microprocessor issues all required information to the controller to perform a specific operation. execution the controller performs the specified operation. result after the operation is completed, status information and other housekeeping information is provided to the microprocessor. fdc commands command symbol descriptions: c: cylinder number 0 - 256 d: data pattern dir: step direction dir = 0, step out dir = 1, step in ds0: disk drive select 0 ds1: disk drive select 1 dtl: data length ec: enable count eot: end of track efifo: enable fifo eis: enable implied seek eot: end of track fifothr: fifo threshold gap: gap length selection gpl: gap length h: head number hds: head number select hlt: head load time hut: head unload time lock: lock efifo, fifothr, ptrtrk bits prevent affected by software reset mfm: mfm or fm mode mt: multitrack n: the number of data bytes written in a sector ncn: new cylinder number nd: non-dma mode ow: overwritten pcn: present cylinder number poll: polling disable pretrk: precompensation start track number r: record rcn: relative cylinder number r/w: read/write sc: sector/per cylinder sk: skip deleted data address mark srt: step rate time st0: status register 0 st1: status register 1 st2: status register 2
25 st3: status register 3 wg: write gate alters timing of we (1) read data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
26 (2) read deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
27 (3) read a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system; fdd reads contents of all cylinders from index hole to eot result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
28 (4) read id phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ disk status after the command has been completed (5) verify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- -------------------- dtl/sc ------------------- execution no data transfer takes place result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
29 (6) version phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller (7) write data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
30 (8) write deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w w -------------------- eot ----------------------- -------------------- gpl ----------------------- -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
31 (9) format a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- n ------------------------ --------------------- sc ----------------------- bytes/sector sectors/cylinder w w --------------------- gpl --------------------- ---------------------- d ------------------------ gap 3 filler byte execution for each sector repeat: w w w w ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ input sector parameters result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------- undefined ------------------- ---------------- undefined ------------------- ---------------- undefined ------------------- ---------------- undefined ------------------- (10) recalibrate phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt (11) sense interrupt status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command code result r r ---------------- st0 ------------------------- ---------------- pcn ------------------------- status information at the end of each seek operation
32 (12) specify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w w | ---------srt ----------- | --------- hut ---------- | |------------ hlt ----------------------------------| nd (13) seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w w 0 0 0 0 0 hds ds1 ds0 -------------------- ncn ----------------------- execution r head positioned over proper cylinder on diskette (14) configure phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure information w w w 0 0 0 0 0 0 0 0 0 eis efifo poll | ------ fifothr ----| | --------------------pretrk ----------------------- | execution internal registers written (15) relative seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 command codes w w 0 0 0 0 0 hds ds1 ds0 | -------------------- rcn ---------------------------- |
33 (16) dumpreg phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 registers placed in fifo result r r r r r r r r r r ----------------------- pcn-drive 0-------------------- ----------------------- pcn-drive 1 ------------------- ----------------------- pcn-drive 2-------------------- ----------------------- pcn-drive 3 ------------------- --------srt ------------------ | --------- hut -------- ----------- hlt -----------------------------------| nd ------------------------ sc/eot ---------------------- lock 0 d3 d2 d1 d0 gap wg 0 eis efifo poll | ------ fifothr -------- -----------------------pretrk ------------------------- (17) perpendicular mode phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command code w ow 0 d3 d2 d1 d0 gap wg (18) lock phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0 (19) sense drive status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 result r ---------------- st3 ------------------------- status information about disk drive (20) invalid phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w ------------- invalid codes ----------------- invalid codes (no operation- fdc goes to standby state) result r -------------------- st0 ---------------------- st0 = 80h
34 register descriptions there are several status, data, and control registers in LPC61W492. these registers are defined below: address register offset read write base address + 0 base address + 1 base address + 2 base address + 3 sa register sb register td register do register td register base address + 4 ms register dr register base address + 5 dt (fifo) register dt (fifo) register base address + 7 di register cc register status register a (sa register) (read base address + 0) this register is used to monitor several disk interface pins in ps/2 and model 30 modes. in ps/2 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 nwp nindex head ntrak0 step ndrv2 init pending dir init pending (bit 7): this bit indicates the value of the floppy disk interrupt output. ndrv2 (bit 6): 0 a second drive has been installed 1 a second drive has not been installed step (bit 5): this bit indicates the complement of nstep output. ntrak0 (bit 4): this bit indicates the value of ntrak0 input.
35 head (bit 3): this bit indicates the complement of nhead output. 0 side 0 1 side 1 nindex (bit 2): this bit indicates the value of nindex output. nwp (bit 1): 0 disk is write-protected 1 disk is not write-protected dir (bit 0) this bit indicates the direction of head movement. 0 outward direction 1 inward direction in ps/2 model 30 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 wp index head trak0 step f/f drq init pending dir init pending (bit 7): this bit indicates the value of the floppy disk interrupt output. drq (bit 6): this bit indicates the value of drq output pin. step f/f (bit 5): this bit indicates the complement of latched nstep output. trak0 (bit 4): this bit indicates the complement of ntrak0 input.
36 nhead (bit 3): this bit indicates the value of nhead output. 0 side 1 1 side 0 index (bit 2): this bit indicates the complement of nindex output. wp (bit 1): 0 disk is not write-protected 1 disk is write-protected ndir (bit 0) this bit indicates the direction of head movement. 0 inward direction 1 outward direction status register b (sb register) (read base address + 1) this register is used to monitor several disk interface pins in ps/2 and model 30 modes. in ps/2 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 mot en a we rdata toggle wdata toggl e drive sel0 mot en b 1 1 drive sel0 (bit 5): this bit indicates the status of do register bit 0 (drive select bit 0). wdata toggle (bit 4): this bit changes state at every rising edge of the nwd output pin. rdata toggle (bit 3): this bit changes state at every rising edge of the nrdata output pin. we (bit 2): this bit indicates the complement of the nwe output pin. mot en b (bit 1) this bit indicates the complement of the nmob output pin. mot en a (bit 0) this bit indicates the complement of the nmoa output pin. in ps/2 model 30 mode, the bit definitions for this register are as follows:
37 1 2 3 4 5 6 7 0 dsc dsd we f/f rdata f/f dsa dsb drv2 wd f/f ndrv2 (bit 7): 0 a second drive has been installed 1 a second drive has not been installed ndsb (bit 6): this bit indicates the status of ndsb output pin. ndsa (bit 5): this bit indicates the status of ndsa output pin. wd f/f(bit 4): this bit indicates the complement of the latched nwd output pin at every rising edge of the nwd output pin. rdata f/f(bit 3): this bit indicates the complement of the latched nrdata output pin. we f/f (bit 2): this bit indicates the complement of latched nwe output pin. ndsd (bit 1): 0 drive d has been selected 1 drive d has not been selected ndsc (bit 0): 0 drive c has been selected 1 drive c has not been selected
38 digital output register (do register) (write base address + 2) the digital output register is a write-only register controlling drive motors, drive selection, drq/irq enable, and fdc resetting. all the bits in this register are cleared by the mr pin. the bit definitions are as follows: 76 54 3 2 1-0 drive select: 00 select drive a 01 select drive b 10 select drive c 11 select drive d floppy disk controller reset active low resets fdc dma and int enable active high enable drq/irq motor enable a. motor a on when active high motor enable b. motor b on when active high motor enable c. motor c on when active high motor enable d. motor d on when active high tape drive register (td register) (read base address + 3) this register is used to assign a particular drive number to the tape drive support mode of the data separator. this register also holds the media id, drive type, and floppy boot drive information of the floppy disk drive. in normal floppy mode, this register includes only bit 0 and 1. the bit definitions are as follows: 1 2 3 4 5 6 7 0 tape sel 0 tape sel 1 xx xx x x if three mode fdd function is enabled (en3mode = 1 in cr9), the bit definitions are as follows: 1 2 3 4 5 6 7 0 floppy boot drive 0 floppy boot drive 1 drive type id0 drive type id1 media id0 media id1 tape sel 0 tape sel 1
39 media id1 media id0 (bit 7, 6): these two bits are read only. these two bits reflect the value of cr8 bit 3, 2. drive type id1 drive type id0 (bit 5, 4): these two bits reflect two of the bits of cr7. which two bits are reflected depends on the last drive selected in the do register. floppy boot drive 1, 0 (bit 3, 2): these two bits reflect the value of cr8 bit 1, 0. tape sel 1, tape sel 0 (bit 1, 0): these two bits assign a logical drive number to the tape drive. drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. tape sel 1 tape sel 0 drive selected 0 0 none 0 1 1 1 0 2 1 1 3 main status register (ms register) (read base address + 4) the main status register is used to control the flow of data between the microprocessor and the controller. the bit definitions for this register are as follows: fdd 0 busy, (d0b = 1), fdd number 0 is in the seek mode. fdd 1 busy, (d1b = 1), fdd number 1 is in the seek mode. fdc busy, (cb). a read or write command is in the process when cb = high. non-dma mode, the fdc is in the non-dma mode, this bit is set only during the execution phase in non-dma mode. transition to low state indicates execution phase has ended. data input/output, (dio). if dio= high then transfer is from data register to the processor. if dio = low then transfer is from processor to data register. request for master (rqm). a high on this bit indicates data register is ready to send or receive data to or from the processor. 7 6 5 4 321 0 fdd 2 busy, (d2b = 1), fdd number 2 is in the seek mode. fdd 3 busy, (d3b = 1), fdd number 3 is in the seek mode. data rate register (dr register) (write base address + 4) the data rate register is used to set the transfer rate and write precompensation. the data rate of the fdc is programmed by the cc register for pc-at and ps/2 model 30 and ps/2 mode, and not by the dr register. the real data rate is determined by the most recent write to either of the dr register or cc register.
40 1 2 3 4 5 6 7 0 drate0 drate1 precomp0 precomp1 precomp2 power dow n s/w reset 0 s/w reset (bit 7): this bit is the software reset bit. power-down (bit 6): 0 fdc in normal mode 1 fdc in power-down mode precomp2 precomp1 precomp0 (bit 4, 3, 2): these three bits select the value of write precompensation. the following tables show the precompensation values for the combination of these bits. precomp precompensation delay 2 1 0 250k - 1 mbps 2 mbps tape drive 0 0 0 default delays default delays 0 0 1 41.67 ns 20.8 ns 0 1 0 83.34 ns 41.17 ns 0 1 1 125.00 ns 62.5ns 1 0 0 166.67 ns 83.3 ns 1 0 1 208.33 ns 104.2 ns 1 1 0 250.00 ns 125.00 ns 1 1 1 0.00 ns (disabled) 0.00 ns (disabled) data rate default precompensation delays 250 kb/s 125 ns 300 kb/s 125 ns 500 kb/s 125 ns 1 mb/s 41.67ns 2 mb/s 20.8 ns
41 drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc and reduced write current control. 00 500 kb/s (mfm), 250 kb/s (fm), nrwc = 1 01 300 kb/s (mfm), 150 kb/s (fm), nrwc = 0 10 250 kb/s (mfm), 125 kb/s (fm), nrwc = 0 11 1 mb/s (mfm), illegal (fm), nrwc= 1 the 2 mb/s data rate for tape drive is only supported by setting 01 to drate1 and drate0 bits, as well as setting 10 to drt1 and drt0 bits which are two of the configure register crf4 or crf5 bits in logic device 0. please refer to the function description of crf4 or crf5 and data rate table for individual data rates setting. fifo register (r/w base address + 5) the data register consists of four status registers in a stack with only one register presented to the data bus at a time. this register stores data, commands, and parameters and provides diskette-drive status information. data bytes are passed through the data register to program or obtain results after a command. in the LPC61W492, this register defaults to fifo disabled mode after reset. the fifo can change its value and enable its operation through the configure command. status register 0 (st0) 7-6 5 4 3 2 1-0 us1, us0 drive select: 00 drive a selected 01 drive b selected 10 drive c selected 11 drive d selected hd head address: 1 head selected 0 head selected nr not ready: 1 drive is not ready 0 drive is ready ec equipment check: 1 when a fault signal is received from the fdd or the track 0 signal fails to occur after 77 step pulses 0 no error se seek end: 1 seek end 0 seek error ic interrupt code: 00 normal termination of command 01 abnormal termination of command 10 invalid command issue 11 abnormal termination because the ready signal from fdd changed state during command execution
42 status register 1 (st1) missing address mark. 1 when the fdc cannot detect the data address mark or the data address mark has been deleted. nw (not writable). 1 if a write protect signal is detected from the diskette drive during execution of write data. nd (no data). 1 if specified sector cannot be found during execution of a read, write or verifly data. not used. this bit is always 0. or (over rum). 1 if the fdc is not serviced by the host system within a certain time interval during data transfer . de (data error).1 when the fdc detects a crc error in either the id field or the data field. not used. this bit is always 0. en (end of track). 1 when the fdc tries to access a sector beyond the final sector of a cylinder. 0 1 2 3 4 5 6 7 status register 2 (st2) 1 2 3 4 5 6 70 bc (bad cylinder) md (missing address mark in data field). 1 if the fdc cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 no error 1 bad cylinder 0 no error sn (scan not satisfied) 1 during execution of the scan command 0 no error sh (scan equal hit) 1 during execution of the scan command, if the equal condition is satisfied 0 no error wc (wrong cylinder) 1 indicates wrong cylinder dd (data error in the data field) 1 if the fdc detects a crc error in the data field 0 no error cm (control mark) 1 during execution of the read data or scan command 0 no error not used. this bit is always 0 status register 3 (st3) 1 2 3 4 5 6 7 0 us0 unit select 0 us1 unit select 1 hd head address ts two-side to track 0 ry ready wp write protected ft fault
43 digital input register (di register) (read base address + 7) the digital input register is an 8-bit read-only register used for diagnostic purposes. in a pc/xt or at only bit 7 is checked by the bios. when the register is read, bit 7 shows the complement of ndskchg, while other bits of the data bus remain in tri-state. bit definitions are as follows: x x x x x x x x 0 1 2 3 4 5 6 7 reserved for the hard disk controller during a read of this register, these bits are in tri-state dskchg in the ps/2 mode, the bit definitions are as follows: 1 2 3 4 5 6 7 0 high dens drate0 drate1 dskchg 11 1 1 dskchg (bit 7): this bit indicates the complement of the ndskchg input. bit 6-3: these bits are always a logic 1 during a read. drate1 drate0 (bit 2, 1): these two bits select the data rate of the fdc. refer to the dr register bits 1 and 0 for the settings corresponding to the individual data rates. nhigh dens (bit 0): 0 500 kb/s or 1 mb/s data rate (high density fdd) 1 250 kb/s or 300 kb/s data rate in the ps/2 model 30 mode, the bit definitions are as follows: 1 2 3 4 5 6 7 0 drate0 drate1 dskchg noprec dmaen 00 0
44 dskchg (bit 7): this bit indicates the status of ndskchg input. bit 6-4: these bits are always a logic 1 during a read. dmaen (bit 3): this bit indicates the value of do register bit 3. noprec (bit 2): this bit indicates the value of cc register noprec bit. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc. configuration control register (cc register) (write base address + 7) this register is used to control the data rate. in the pc/at and ps/2 mode, the bit definitions are as follows: xxxx xx drate0 drate1 0 1 2 3 4 5 7 6 x: reserved bit 7-2: reserved. these bits should be set to 0. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc. in the ps/2 model 30 mode, the bit definitions are as follows: 1 2 3 4 5 6 7 0 drate0 drate1 noprec xx xx x x: reserved bit 7-3: reserved. these bits should be set to 0. noprec (bit 2): this bit indicates no precompensation. it has no function and can be set by software. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc.
45 uart port universal asynchronous receiver/transmitter (uart a, uart b) the uarts are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. the serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. the uarts are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this 16x clock to drive the receiver logic. the uarts also support the midi data rate. furthermore, the uarts also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. the uarts have a fifo mode to reduce the number of interrupts presented to the cpu. in each uart, there are 16-byte fifos for both receive and transmit mode. register address uart control register (ucr) (read/write) the uart control register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection. 1 2 3 4 5 6 7 0 data length select bit 0 (dls0) data length select bit 1(dls1) multiple stop bits enable (msbe) parity bit enable (pbe) even parity enable (epe) parity bit fixed enable (pbfe) set silence enable (sse) baudrate divisor latch access bit (bdlab) bit 7: bdlab. when this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. when this bit is reset, the receiver buffer register, the transmitter buffer register, or the interrupt control register can be accessed. bit 6: sse. a logical 1 forces the serial output (sout) to a silent state (a logical 0). only irtx is affected by this bit; the transmitter is not affected. bit 5: pbfe. when pbe and pbfe of ucr are both set to a logical 1, (1) if epe is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if epe is logical 0, the parity bit is fixed as logical 1 to transmit and check.
46 uart register bit map bit number register address base 0 1 2 3 4 5 6 7 + 0 bdlab = 0 receiver buffer register (read only) rbr rx data bit 0 rx data bit 1 rx data bit 2 rx data bit 3 rx data bit 4 rx data bit 5 rx data bit 6 rx data bit 7 + 0 bdlab = 0 transmitter buffer register (write only) tbr tx data bit 0 tx data bit 1 tx data bit 2 tx data bit 3 tx data bit 4 tx data bit 5 tx data bit 6 tx data bit 7 + 1 bdlab = 0 interrupt control register icr rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) usr interrupt enable (eusri) hsr interrupt enable (ehsri) 0 0 0 0 + 2 interrupt status register (read only) isr "0" if interrupt pending interrupt status bit (0) interrupt status bit (1) interrupt status bit (2)** 0 0 fifos enabled ** fifos enabled ** + 2 uart fifo control register (write only) ufr fifo enable rcvr fifo reset xmit fifo reset dma mode select reserved reversed rx interrupt active level (lsb) rx interrupt active level (msb) + 3 uart control register ucr data length select bit 0 (dls0) data length select bit 1 (dls1) multiple stop bits enable (msbe) parity bit enable (pbe) even parity enable (epe) parity bit fixed enable pbfe) set silence enable (sse) baudrate divisor latch access bit (bdlab) + 4 handshake control register hcr data terminal ready (dtr) request to send (rts) loopback ri input irq enable internal loopback enable 0 0 0 + 5 uart status register usr rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) tbr empty (tbre) tsr empty (tsre) rx fifo error indication (rfei) ** + 6 handshake status register hsr cts toggling (tcts) dsr toggling (tdsr) ri falling edge (feri) dcd toggling (tdcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) + 7 user defined register udr bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 + 0 bdlab = 1 baudrate divisor latch low bll bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
47 + 1 bdlab = 1 baudrate divisor latch high bhl bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 *: bit 0 is the least significant bit. the least significant bit is the first bit serially transmitted or received. **: these bits are always 0 in 16450 mode. bit 4: epe. this bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. when this bit is set, an even number of logic 1's are sent or checked. when the bit is reset, an odd number of logic 1's are sent or checked. bit 3: pbe. when this bit is set, the position between the last data bit and the stop bit of the sout will be stuffed with the parity bit at the transmitter. for the receiver, the parity bit in the same position as the transmitter will be detected. bit 2: msbe. this bit defines the number of stop bits in each serial character that is transmitted or received. (1) if msbe is set to a logical 0, one stop bit is sent and checked. (2) if msbe is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) if msbe is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. bits 0 and 1: dls0, dls1. these two bits define the number of data bits that are sent or checked in each serial character. word length definition dls1 dls0 data length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits uart status register (usr) (read/write) this 8-bit register provides information about the status of the data transfer during communication. 1 2 3 4 5 6 70 rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) transmitter buffer register empty (tbre) transmitter shift register empty (tsre) rx fifo error indication (rfei) bit 7: rfei. in 16450 mode, this bit is always set to a logic 0. in 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the fifo. in 16550 mode, this bit is cleared by reading from the usr if there are no remaining errors left in the fifo.
48 bit 6: tsre. in 16450 mode, when tbr and tsr are both empty, this bit will be set to a logical 1. in 16550 mode, if the transmit fifo and tsr are both empty, it will be set to a logical 1. other thanthese two cases, this bit will be reset to a logical 0. bit 5: tbre. in 16450 mode, when a data character is transferred from tbr to tsr, this bit will be set to a logical 1. if etrei of icr is a logical 1, an interrupt will be generated to notify the cpu to write the next data. in 16550 mode, this bit will be set to a logical 1 when the transmit fifo is empty. it will be reset to a logical 0 when the cpu writes data into tbr or fifo. bit 4: sbd. this bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 3: nser. this bit is set to a logical 1 to indicate that the received data have no stop bit. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 2: pber. this bit is set to a logical 1 to indicate that the parity bit of received data is wrong. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 1: oer. this bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the cpu. in 16550 mode, it indicates the same condition instead of fifo full. when the cpu reads usr, it will clear this bit to a logical 0. bit 0: rdr. this bit is set to a logical 1 to indicate received data are ready to be read by the cpu in the rbr or fifo. after no data are left in the rbr or fifo, the bit will be reset to a logical 0. handshake control register (hcr) (read/write) this register controls the pins of the uart used for handshaking peripherals such as modem, and controls the diagnostic mode of the uart. 0 0 0 0 1 2 3 4 5 6 7 data terminal ready (dtr) request to send (rts) loopback ri input irq enable internal loopback enable bit 4: when this bit is set to a logical 1, the uart enters diagnostic mode by an internal loopback, as follows: (1) sout is forced to logical 1, and sin is isolated from the communication link instead of the tsr. (2) modem output pins are set to their inactive state. (3) modem input pins are isolated from the communication link and connect internally as dtr (bit 0 of hcr) ( ndsr , rts ( bit 1 of hcr) ( ncts , loopback ri input (bit 2 of hcr) ( nri and irq enable ( bit 3 of hcr) ( ndcd . aside from the above connections, the uart operates normally. this method allows the cpu to test the uart in a convenient way. bit 3: the uart interrupt output is enabled by setting this bit to a logic 1. in the diagnostic mode this bit is internally connected to the modem control input ndcd.
49 bit 2: this bit is used only in the diagnostic mode. in the diagnostic mode this bit is internally connected to the modem control input nri. bit 1: this bit controls the nrts output. the value of this bit is inverted and output to nrts. bit 0: this bit controls the ndtr output. the value of this bit is inverted and output to ndtr. handshake status register (hsr) (read/write) this register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins. 1 2 3 4 5 6 70 ri falling edge (feri) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) cts toggling (tcts) dsr toggling (tdsr) dcd toggling (tdcd) bit 7: this bit is the opposite of the ndcd input. this bit is equivalent to bit 3 of hcr in loopback mode. bit 6: this bit is the opposite of the nri input. this bit is equivalent to bit 2 of hcr in loopback mode. bit 5: this bit is the opposite of the ndsr input. this bit is equivalent to bit 0 of hcr in loopback mode. bit 4: this bit is the opposite of the ncts input. this bit is equivalent to bit 1 of hcr in loopback mode. bit 3: tdcd. this bit indicates that the ndcd pin has changed state after hsr was read by the cpu. bit 2: feri. this bit indicates that the nri pin has changed from low to high state after hsr was read by the cpu. bit 1: tdsr. this bit indicates that the ndsr pin has changed state after hsr was read by the cpu. bit 0: tcts. this bit indicates that the ncts pin has changed state after hsr was read. uart fifo control register (ufr) (write only) this register is used to control the fifo functions of the uart. 1 2 3 4 5 6 70 fifo enable receiver fifo reset transmitter fifo reset dma mode select reserved reserved rx interrupt active level (lsb) rx interrupt active level (msb)
50 bit 6, 7: these two bits are used to set the active level for the receiver fifo interrupt. for example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver fifo, the interrupt will be activated to notify the cpu to read the data from the fifo. fifo trigger level bit 7 bit 6 rx fifo interrupt active level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14 bit 4, 5: reserved bit 3: when this bit is programmed to logic 1, the dma mode will change from mode 0 to mode 1 if ufr bit 0 = 1. bit 2: setting this bit to a logical 1 resets the tx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. bit 1: setting this bit to a logical 1 resets the rx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. bit 0: this bit enables the 16550 (fifo) mode of the uart. this bit should be set to a logical 1 before other bits of ufr are programmed. interrupt status register (isr) (read only) this register reflects the uart interrupt status, which is encoded by different interrupt sources into 3 bits. 1 2 3 4 5 6 7 0 0 if interrupt pending interrupt status bit 0 interrupt status bit 1 interrupt status bit 2 fifos enabled fifos enabled 00 bit 7, 6: these two bits are set to a logical 1 when ufr bit 0 = 1. bit 5, 4: these two bits are always logic 0. bit 3: in 16450 mode, this bit is 0. in 16550 mode, both bit 3 and 2 are set to a logical 1 when a time- out interrupt is pending. bit 2, 1: these two bits identify the priority level of the pending interrupt, as shown in the table below. bit 0: this bit is a logical 1 if there is no interrupt pending. if one of the interrupt sources has occurred, this bit will be set to a logical 0.
51 interrupt control function isr interrupt set and function bit 3 bit 2 bit 1 bit 0 interrupt priority interrupt type interrupt source clear interrupt 0 0 0 1 - - no interrupt pending - 0 1 1 0 first uart receive status 1. oer = 1 2. pber =1 3. nser = 1 4. sbd = 1 read usr 0 1 0 0 second rbr data ready 1. rbr data ready 2. fifo interrupt active level reached 1. read rbr 2. read rbr until fifo data under active level 1 1 0 0 second fifo data timeout data present in rx fifo for 4 characters period of time since last access of rx fifo. read rbr 0 0 1 0 third tbr empty tbr empty 1. write data into tbr 2. read isr (if priority is third) 0 0 0 0 fourth handshake status 1. tcts = 1 2. tdsr = 1 3. feri = 1 4. tdcd = 1 read hsr ** bit 3 of isr is enabled when bit 0 of ufr is logical 1. interrupt control register (icr) (read/write) this 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. the interrupt system can be totally disabled by resetting bits 0 through 3 of the interrupt control register (icr). a selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 000 1 2 3 4 5 6 7 0 0 rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) uart receive status interrupt enable (eusri) handshake status interrupt enable (ehsri) bit 7-4: these four bits are always logic 0. bit 3: ehsri. setting this bit to a logical 1 enables the handshake status register interrupt. bit 2: eusri. setting this bit to a logical 1 enables the uart status register interrupt. bit 1: etbrei. setting this bit to a logical 1 enables the tbr empty interrupt. bit 0: erdri. setting this bit to a logical 1 enables the rbr data ready interrupt. programmable baud generator (bll/bhl) (read/write) two 8-bit registers, bll and bhl, compose a programmable baud generator that uses 24 mhz to generate a 1.8461 mhz frequency and divides it by a divisor from 1 to 2 16 -1. the output frequency of
52 the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. the table in the next page illustrates the use of the baud generator with a frequency of 1.8461 mhz. in high-speed uart mode (refer to cr0c bit7 and cr0c bit6), the programmable baud generator directly uses 24 mhz and the same divisor as the normal speed divisor. in high-speed mode, the data transmission rate can be as high as 1.5mbps. user-defined register (udr) (read/write) this is a temporary register that can be accessed and defined by the user. baud rate table baud rate from different pre-divider pre-div: 13 1.8461mhz pre-div:1.625 14.769mhz pre-div: 1.0 24mhz decimal divisor used to generate 16x clock error percentage between desired and actual 50 400 650 2304 ** 75 600 975 1536 ** 110 880 1430 1047 0.18% 134.5 1076 1478.5 857 0.099% 150 1200 1950 768 ** 300 2400 3900 384 ** 600 4800 7800 192 ** 1200 9600 15600 96 ** 1800 14400 23400 64 ** 2000 16000 26000 58 0.53% 2400 19200 31200 48 ** 3600 28800 46800 32 ** 4800 38400 62400 24 ** 7200 57600 93600 16 ** 9600 76800 124800 12 ** 19200 153600 249600 6 ** 38400 307200 499200 3 ** 57600 460800 748800 2 ** 115200 921600 1497600 1 ** ** the percentage error for all baud rates, except where indicated otherwise, is 0.16%. note. pre-divisor is determined by crf0 of uart a and b.
53 cir receiver port cir registers bank0.reg0 - receiver buffer registers (rbr) (read) receiver buffer register is read only. when the cir pulse train has been detected and passed by the internal signal filter, the data samped and shifted into shifter register will write into receiver buffer register. in the cir, this port is only supports pio mode and the address port is defined in the pnp. bank0.reg1 - interrupt control register (icr) power on default <7:0> = 00000000 binary bit name read/write description 7 en_glbi read/write enable global interrupt. write 1, enable interrupt. write 0, disable global interrupt. 6-3 reserved - reserved 2 en_tmr_i read/write enable timer interrupt. 1 en_lsr_i read/write enable line-status-register interrupt. 0 en_rx_i read/write receiver thershold-level interrupt enable. bank0.reg2 - interrupt status register (isr) power on default <7:0> = 00000000 binary bit name read/write description 7-3 reserved reserved 2 tmr_i read only timer interrupt. set to 1 when timer count to 0. this bit will be affected by (1) the timer registers are defined in bank4.reg0 and bank1.reg0~1, (2) en_tmr(enable timer, in bank0.reg3.bit2) should be set to 1, (3) entmr_i (enable timer interrupt, in bank0.reg1.bit2) should be set to 1. 1 lsr_i read only line-status-register interrupt. set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the line status register (lsr) sets to 1. clear to 0 when lsr is read. 0 rxth_i read only receiver thershold-level interrupt. set to 1 when (1) the receiver buffer register (rbr) is equal or larger than the threshold level, (2) rbr occurs time-out if the receiver buffer register has valid data and below the threshold level. clear to 0 when rbr is less than threshold level from reading rbr.
54 bank0~3.reg3 - cir control register 0/bank select register (ctr0/bsr) (bank0~3) power on default <7:0> = 00000000 binary bit name read/write description 7-6 bnk_sel<1:0> read/write bank select register. these two bits are shared same address so that bank select register (bsr) can be programmed to desired bank in any bank. bnk_sel<1:0> = 00 select bank 0. bnk_sel<1:0> = 01 select bank 1. bnk_sel<1:0> = reserved. bnk_sel<1:0> = reserved. 5-4 rxftl1/0 read/write receiver fifo threshold level. it is to determine the rxth_i to become 1 when the receiver fifo threshold level is equal or larger than the defined value shown as follow. rxftl<1:0> = 00 -- 1 byte rxftl<1:0> = 01 -- 4 bytes rxftl<1:0> = 10 -- 8 bytes rxftl<1:0> = 11 -- 14 bytes 3 tmr_tst read/write timer test. write to 1, then reading the tmrl/tmrh will return the programmed values of tmrl/tmrh, that is, does not return down count counter value. this bit is for test timer register. 2 en_tmr read/write enable timer. write to 1, enable the timer 1 rxf_rst read/write setting this bit to a logical 1 resets the rx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. 0 tmr_clk read/write timer input clock. smsc test register bank0.reg4 - cir control register (ctr) power on default <7:0> = 0010,1001 binary bit name read/write description 7-5 rx_fr<2:0> read/write receiver frequency range 2~0. these bits select the input frequency of the receiver ranges. for the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. 4-0 rx_fsl<4:0> read/write receiver frequency select 4~0. select the receiver operation frequency.
55 low frequency range select of receiver. rx_fr2~0 (low frequency) 001 010 011 rx_fsl4~0 min. max. min. max. min. max. 00010 26.1 29.6 24.7 31.7 23.4 34.2 00011 28.2 32.0 26.7 34.3 25.3 36.9 00100 29.4 33.3 27.8 35.7 26.3 38.4 00101 30.0 34.0 28.4 36.5 26.9 39.3 00110 31.4 35.6 29.6 38.1 28.1 41.0 00111 32.1 36.4 30.3 39.0 28.7 42.0 01000 32.8 37.2 31.0 39.8 29.4 42.9 01001 33.6* 38.1* 31.7 40.8 30.1 44.0 01011 34.4 39.0 32.5 41.8 30.8 45.0 01100 36.2 41.0 34.2 44.0 32.4 47.3 01101 37.2 42.1 35.1 45.1 33.2 48.6 01111 38.2 43.2 36.0 46.3 34.1 49.9 10000 40.3 45.7 38.1 49.0 36.1 52.7 10010 41.5 47.1 39.2 50.4 37.2 54.3 10011 42.8 48.5 40.4 51.9 38.3 56.0 10101 44.1 50.0 41.7 53.6 39.5 57.7 10111 45.5 51.6 43.0 55.3 40.7 59.6 11010 48.7 55.2 46.0 59.1 43.6 63.7 11011 50.4 57.1 47.6 61.2 45.1 65.9 11101 54.3 61.5 51.3 65.9 48.6 71.0 note that the other non-defined values are reserved. bank0.reg5 - uart line status register (usr) power on default <7:0> = 0000,0000 binary bit name read/write description 7-3 reserved - - 2 rx_to read/write set to 1 when receiver fifo or frame status fifo occurs time- out. read this bit will be cleared. 1 ov_err read/write received fifo overrun. read to clear. 0 rdr read/write this bit is set to a logical 1 to indicate received data are ready to be read by the cpu in the rbr or fifo. after no data are left in the rbr or fifo, the bit will be reset to a logical 0.
56 bank0.reg6 - remote infrared config register (rir_cfg) power on default <7:0> = 0000,0000 binary bit name read/write description 7-6 smpsel<1:0> read/write sampling mode select. select internal decoder methodology from the internal filter. selected decoder mode will determine the receive data format. the sampling mode is shown as bellow: smpsel<1:0> = 00 t-period sample mode. smpsel<1:0> = 01 over-sampling mode. smpsel<1:0> = 10 over-sampling with re-sync. smpsel<1:0> = 11 fifo test mode. the t-period code format is defined as follows. b7 b6 b5 b4 b2 b1 b0 b3 bit value (number of bits) - 1 the bit value is set to 0, then the high pulse will be received. the bit value is set to 1, then no energy will be received. the opposite results will be generated when the bit rxinv (bank0.reg6.bit0) is set to 1. 5-4 lp_sl<1:0> read/write low pass filter source selcetion. lp_sl<1:0> = 00 select raw irrx signal. lp_sl<1:0> = 01 select r.b.p. signal lp_sl<1:0> = 10 select d.b.p. signal. lp_sl<1:0> = 11 reserved. 3-2 rxdmsl<1:0> read/write receiver demodulation source selection. rxdmsl<1:0> = 00 select b.p. and l.p. filter. rxdmsl<1:0> = 01 select b.p. but not l.p. rxdmsl<1:0> = 10 reserved. rxdmsl<1:0> = 11 do not pass demodulation. 1 pre_div read/write baud rate pre-divisor. set to 1, the baud rate generator input clock is set to 1.8432m hz which is set to pre-divisor into 13. when set to 0, the pre-divisor is set to 1, that is, the input clock of baud rate generator is set to 24m hz. 0 rxinv read/write receiving signal invert. write to 1, invert the receiving signal.
57 bank0.reg7 - user defined register (udr/audr) power on default <7:0> = 0000,0000 binary bit name read/write description 7 rxact read/write receive active. set to 1 whenever a pulse or pulse-train is detected by the receiver. if a 1 is written into the bit position, the bit is cleared and the receiver is de-actived. when this bit is set, the receiver samples the ir input continuously at the programmed baud rate and transfers the data to the receiver fifo. 6 rx_pd read only set to 1 whenever a pulse or pulse-train (modulated pulse) is detected by the receiver. can be used by the sofware to detect idle condition cleared upon read. 5 reserved - - 4-0 folval read only fifo level value. indicate that how many bytes are there in the current received fifo. can read these bits then get the fifo level value and successively read rbr by the prior value.
58 bank1.reg0~1 - baud rate divisor latch (bll/bhl) the two registers of bll and bhl are baud rate divisor latch in the legacy uart/sir/ask-ir mode. read/write these registers, if set in advanced uart mode, will occur backward operation, that is, will go to legacy uart mode and clear some register values shown table as follows. baud rate table baud rate using 24 mhz to generate 1.8461 mhz desired baud rate decimal divisor used to generate 16x clock percent error difference between desired and actual 50 2304 ** 75 1536 ** 110 1047 0.18% 134.5 857 0.099% 150 768 ** 300 384 ** 600 192 ** 1200 96 ** 1800 64 ** 2000 58 0.53% 2400 48 ** 3600 32 ** 4800 24 ** 7200 16 ** 9600 12 ** 19200 6 ** 38400 3 ** 57600 2 ** 115200 1 ** 1.5m 1 (note 1) 0% note 1: only use in high speed mode, when bank0.reg6.bit7 is set. ** the percentage error for all baud rates, except where indicated otherwise, is 0.16%
59 bank1.reg2 - version id regiister i (vid) power on default <7:0> = 0001,0000 binary bit name read/write description 7-0 vid read only version id, default is set to 0x10. bank0~3.reg3 - cir control register 0/bank select register (ctr0/bsr) (bank0~3) this register is defined same as in bank0.reg3. bank1.reg4 - timer low byte register (tmrl) power on default <7:0> = 0000,0000 binary bit name read/write description 7-0 tmrl read/write timer low byte register. this is a 12-bit timer (another 4-bit is defined in bank1.reg5) which resolution is 1 ms, that is, the programmed maximum time is 2 12 -1 ms. the timer is a down- counter. the timer start down count when the bit en_tmr (enable timer) of bank0.reg2. is set to 1. when the timer down count to zero and en_tmr=1, the tmr_i is set to 1. when the counter down count to zero, a new initial value will be re-loaded into timer counter. bank1.reg5 - timer high byte register (tmrh) power on default <7:0> = 0000,0000 binary bit name read/write description 7-4 reserved reserved. 3-0 tmrh read/write timer high byte register. see bank1.reg4.
60 parallel port printer interface logic the parallel port of the LPC61W492 makes possible the attachment of various devices that accept eight bits of parallel data at standard ttl level. the LPC61W492 supports an ibm xt/at compatible parallel port (spp), bi-directional parallel port (bpp), enhanced parallel port (epp), extended capabilities parallel port (ecp), extension fdd mode (extfdd), extension 2fdd mode (ext2fdd) on the parallel port. refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. the following table shows the pin definitions for different modes of the parallel port. parallel port connector and pin definitions host connector pin number of LPC61W492 pin attribute spp epp ecp 1 36 o nstb nwrite nstb, hostclk 2 2-9 31-26, 24-23 i/o pd<0:7> pd<0:7> pd<0:7> 10 22 i nack intr nack, periphclk 2 11 21 i busy nwait busy, periphack 2 12 19 i pe pe peerror, nackreverse 2 13 18 i slct select slct, xflag 2 14 35 o nafd ndstrb nafd, hostack 2 15 34 i nerr nerror nfault 1 , nperiphrequest 2 16 33 o ninit ninit ninit 1 , nreverserqst 2 17 32 o nslin nastrb nslin 1 , ecpmode 2 notes: n : active low 1. compatible mode 2. high speed mode 3. for more information, refer to the ieee 1284 standard.
61 parallel port connector and pin definitions host connector pin number of LPC61W492 pin attribute spp pin attribut e ext2fdd pin attribute extfdd 1 36 o nstb --- --- --- --- 2 31 i/o pd0 i nindex2 i nindex2 3 30 i/o pd1 i ntrak02 i ntrak02 4 29 i/o pd2 i nwp2 i nwp2 5 28 i/o pd3 i nrdata2 i nrdata2 6 27 i/o pd4 i ndskchg2 i ndskchg2 7 26 i/o pd5 --- --- --- --- 8 24 i/o pd6 od nmoa2 --- --- 9 23 i/o pd7 od ndsa2 --- --- 10 22 i nack od ndsb2 od ndsb2 11 21 i busy od nmob2 od nmob2 12 19 i pe od nwd2 od nwd2 13 18 i slct od nwe2 od nwe2 14 35 o nafd od nrwc2 od nrwc2 15 34 i nerr od nhead2 od nhead2 16 33 o ninit od ndir2 od ndir2 17 32 o nsli n od nstep2 od nstep2 enhanced parallel port (epp) printer mode and epp register address a2 a1 a0 register note 0 0 0 data port (r/w) 1 0 0 1 printer status buffer (read) 1 0 1 0 printer control latch (write) 1 0 1 0 printer control swapper (read) 1 0 1 1 epp address port (r/w) 2 1 0 0 epp data port 0 (r/w) 2 1 0 1 epp data port 1 (r/w) 2 1 1 0 epp data port 2 (r/w) 2 1 1 1 epp data port 2 (r/w) 2 notes: 1. these registers are available in all modes. 2. these registers are available only in epp mode. data swapper the system microprocessor can read the contents of the printer's data latch by reading the data swapper. printer status buffer the system microprocessor can read the printer status by reading the address of the printer status buffer. the bit definitions are as follows:
62 1 11 2 3 54 6 70 tmout error slct pe busy ack bit 7: this signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. when this signal is active, the printer is busy and cannot accept data. bit 6: this bit represents the current state of the printer's nack signal. a 0 means the printer has received a character and is ready to accept another. normally, this signal will be active for approximately 5 microseconds before busy# stops. bit 5: logical 1 means the printer has detected the end of paper. bit 4: logical 1 means the printer is selected. bit 3: logical 0 means the printer has encountered an error condition. bit 1, 2: these two bits are not implemented and are logic one during a read of the status register. bit 0: this bit is valid in epp mode only. it indicates that a 10 ' s time-out has occurred on the epp bus. a logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. printer control latch and printer control swapper the system microprocessor can read the contents of the printer control latch by reading the printer control swapper. bit definitions are as follows: 1 1 1 2 3 4 5 6 70 strobe auto fd slct in irq enable dir init bit 7, 6: these two bits are a logic one during a read. they can be written. bit 5: direction control bit when this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). this bit can be read and written. in spp mode, this bit is invalid and fixed at zero. bit 4: a 1 in this position allows an interrupt to occur when nack changes from low to high. bit 3: a 1 in this bit position selects the printer. bit 2: a 0 starts the printer (50 microsecond pulse, minimum). bit 1: a 1 causes the printer to line-feed after a line is printed.
63 bit 0: a 0.5 microsecond minimum high active pulse clocks data into the printer. valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. epp address port the address port is available only in epp mode. bit definitions are as follows: 1 2 3 4 5 6 70 pd0 pd1 pd2 pd3 pd5 pd4 pd6 pd7 the contents of db0-db7 are buffered (non-inverting) and output to ports pd0-pd7 during a write operation. the leading edge of niow causes an epp address write cycle to be performed, and the trailing edge of niow latches the data for the duration of the epp write cycle. pd0-pd7 ports are read during a read operation. the leading edge of nior causes an epp address read cycle to be performed and the data to be output to the host cpu. epp data port 0-3 these four registers are available only in epp mode. bit definitions of each data port are as follows: 1 2 3 4 5 6 7 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 when accesses are made to any epp data port, the contents of db0-db7 are buffered (non-inverting) and output to the ports pd0-pd7 during a write operation. the leading edge of niow causes an epp data write cycle to be performed, and the trailing edge of niow latches the data for the duration of the epp write cycle. during a read operation, ports pd0-pd7 are read, and the leading edge of nior causes an epp read cycle to be performed and the data to be output to the host cpu.
64 bit map of parallel port and epp registers register 7 6 5 4 3 2 1 0 data port (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 status buffer (read) nbusy nack pe slct nerror 1 1 tmout control swapper (read) 1 1 1 irqen slin ninit nautofd nstrobe control latch (write) 1 1 dir irq slin ninit nautofd nstrobe epp address port r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 0 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 1 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 2 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 3 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp pin descriptions epp name type epp description nwrite o denotes an address or data read or write operation. pd<0:7> i/o bi-directional epp address and data bus. intr i used by peripheral device to interrupt the host. nwait i inactive to acknowledge that data transfer is completed. active to indicate that the device is ready for the next transfer. pe i paper end; same as spp mode. select i printer selected status; same as spp mode. ndstrb o this signal is active low. it denotes a data read or write operation. nerror i error; same as spp mode. ninits o this signal is active low. when it is active, the epp device is reset to its initial operating mode. nastrb o this signal is active low. it denotes an address read or write operation.
65 epp operation when the epp mode is selected in the configuration register, the standard and bi-directional modes are also available. the pdx bus is in the standard or bi-directional mode when no epp read, write, or address cycle is currently being executed. in this condition all output signals are set by the spp control port and the direction is controlled by dir of the control port. a watchdog timer is required to prevent system lockup. the timer indicates that more than 10 ' s have elapsed from the start of the epp cycle to the time n wait is deasserted. the current epp cycle is aborted when a time-out occurs. the time-out condition is indicated in status bit 0. epp operation the epp operates on a two-phase cycle. first, the host selects the register within the device for subsequent operations. second, the host performs a series of read and/or write byte operations to the selected register. four operations are supported on the epp: address write, data write, address read, and data read. all operations on the epp device are performed asynchronously. epp version 1.9 operation the epp read/write operation can be completed under the following conditions: a. if the nwait is active low, when the read cycle (nwrite inactive high, ndstrb/nastrb active low) or write cycle (nwrite active low, ndstrb/nastrb active low) starts, the read/write cycle proceeds normally and will be completed when nwait goes inactive high. b. if nwait is inactive high, the read/write cycle will not start. it must wait until nwait changes to active low, at which time it will start as described above. epp version 1.7 operation the epp read/write cycle can start without checking whether nwait is active or inactive. once the read/write cycle starts, however, it will not terminate until nwait changes from active low to inactive high.
66 extended capabilities parallel (ecp) port this port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ecp is not required. it provides an automatic high burst-bandwidth channel that supports dma for ecp in both the forward (host to peripheral) and reverse (peripheral to host) directions. small fifos are used in both forward and reverse directions to improve the maximum bandwidth requirement. the size of the fifo is 16 bytes. the ecp port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the ecp port supports run-length-encoded (rle) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. hardware support for compression is optional. for more information about the ecp protocol, refer to the extended capabilities port protocol and isa interface standard. ecp register and mode definitions name address i/o ecp modes function data base+000h r/w 000-001 data register ecpafifo base+000h r/w 011 ecp fifo (address) dsr base+001h r all status register dcr base+002h r/w all control register cfifo base+400h r/w 010 parallel port data fifo ecpdfifo base+400h r/w 011 ecp fifo (data) tfifo base+400h r/w 110 test fifo cnfga base+400h r 111 configuration register a cnfgb base+401h r/w 111 configuration register b ecr base+402h r/w all extended control register note: the base addresses are specified by cr23, which are determined by configuration register or hardware setting. mode description 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the cr9 and cr0 to select ecp/epp mode) 101 reserved 110 test mode 111 configuration mode note: the mode selection bits are bit 7-5 of the extended control register.
67 data and ecpafifo port modes 000 (spp) and 001 (ps/2) (data port) during a write operation, the data register latches the contents of the data bus on the rising edge of the input. the contents of this register are output to the pd0-pd7 ports. during a read operation, ports pd0-pd7 are read and output to the host. the bit definitions are as follows: 7 6 5 4 3 2 1 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 mode 011 (ecp fifo-address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits this byte to the peripheral automatically. the operation of this register is defined only for the forward direction. the bit definitions are as follows: 7 6 5 4 3 2 1 0 address or rle address/rle device status register (dsr) these bits are at low level during a read of the printer status register. the bits of this status register are defined as follows: 7 6 5 4 3 2 1 0 nfault select perror nack nbusy 1 11
68 bit 7: this bit reflects the complement of the busy input. bit 6: this bit reflects the nack input. bit 5: this bit reflects the perror input. bit 4: this bit reflects the select input. bit 3: this bit reflects the nfault input. bit 2-0: these three bits are not implemented and are always logic one during a read. device control register (dcr) the bit definitions are as follows: 7 6 5 4 3 2 1 0 11 strobe autofd ninit selectin ackinten direction bit 6, 7: these two bits are logic one during a read and cannot be written. bit 5: this bit has no effect and the direction is always out if mode = 000 or mode = 010. direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. bit 4: interrupt request enable. when this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the nack input. bit 3: this bit is inverted and output to the nslin output. 0 the printer is not selected. 1 the printer is selected. bit 2: this bit is output to the ninit output. bit 1: this bit is inverted and output to the nafd output. bit 0: this bit is inverted and output to the nstb output.
69 cfifo (parallel port data fifo) mode = 010 this mode is defined only for the forward direction. the standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or dmaed from the system to this fifo. transfers to the fifo are byte aligned. ecpdfifo (ecp data fifo) mode = 011 when the direction bit is 0, bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the ecp parallel port protocol. transfers to the fifo are byte aligned. when the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ecp into this fifo. reads or dmas from the fifo will return bytes of ecp data to the system. tfifo (test fifo mode) mode = 110 data bytes may be read, written, or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the parallel port lines. however, data in the tfifo may be displayed on the parallel port data lines. cnfga (configuration register a) mode = 111 this register is a read-only register. when it is read, 10h is returned. this indicates to the system that this is an 8-bit implementation. cnfgb (configuration register b) mode = 111 the bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 1 intrvalue compress irqx 0 irqx 1 irqx 2 bit 7: this bit is read-only. it is at low level during a read. this means that this chip does not support hardware rle compression. bit 6: returns the value on the isa irq line to determine possible conflicts.
70 bit 5-3: reflect the irq resource assigned for ecp port. cnfgb[5:3] irq resource 000 reflect other irq resources selected by pnp register (default) 001 irq7 010 irq9 011 irq10 100 irq11 101 irq14 110 irq15 111 irq5 bit 2-0: these five bits are at high level during a read and can be written. ecr (extended control register) mode = all this register controls the extended ecp parallel port functions. the bit definitions are follows: 7 6 5 4 3 2 1 0 empty full service intr dmaen nerrintren mode mode mode bit 7-5: these bits are read/write and select the mode. 000 standard parallel port mode. the fifo is reset in this mode. 001 ps/2 parallel port mode. this is the same as 000 except that direction may be used to tri- state the data lines and reading the data register returns the value on the data lines and not the value in the data register. 010 parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data are automatically transmitted using the standard parallel port protocol. this mode is useful only when direction is 0. 011 ecp parallel port mode. when the direction is 0 (forward direction), bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and auto transmitted to the peripheral using ecp protocol. when the direction is 1 (reverse direction), bytes are moved from the ecp parallel port and packed into bytes in the ecpdfifo. 100 selects epp mode. in this mode, epp is activated if the epp mode is selected. 101 reserved. 110 test mode. the fifo may be written and read in this mode, but the data will not be transmitted on the parallel port. 111 configuration mode. the confga and confgb registers are accessible at 0x400 and 0x401 in this mode.
71 bit 4: read/write (valid only in ecp mode) 1 disables the interrupt generated on the asserting edge of nfault. 0 enables an interrupt pulse on the high to low edge of nfault. if nfault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. bit 3: read/write 1 enables dma. 0 disables dma unconditionally. bit 2: read/write 1 disables dma and all of the service interrupts. 0 enables one of the following cases of interrupts. when one of the service interrupts has occurred, the serviceintr bit is set to a 1 by hardware. this bit must be reset to 0 to re-enable the interrupts. writing a 1 to this bit will not cause an interrupt. (a) dmaen = 1: during dma this bit is set to a 1 when terminal count is reached. (b) dmaen = 0 direction = 0: this bit is set to 1 whenever there are writeintr threshold or more bytes free in the fifo. (c) dmaen = 0 direction = 1: this bit is set to 1 whenever there are readintr threshold or more valid bytes to be read from the fifo. bit 1: read only 0 the fifo has at least 1 free byte. 1 the fifo cannot accept another byte or the fifo is completely full. bit 0: read only 0 the fifo contains at least 1 byte of data. 1 the fifo is completely empty. bit map of ecp port registers d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nack perror select nfault 1 1 1 1 dcr 1 1 directio ackinten selectin ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue 1 1 1 1 1 1 ecr mode nerrintren dmaen serviceintr full empty notes: 1. these registers are available in all modes. 2. all fifos use one common 16-byte fifo.
72 ecp pin descriptions name type description nstrobe (hostclk) o the nstrobe registers data or address into the slave on the asserting edge during write operations. this signal handshakes with busy. pd<7:0> i/o these signals contains address or data or rle data. nack (periphclk) i this signal indicates valid data driven by the peripheral when asserted. this signal handshakes with nautofd in reverse. busy (periphack) i this signal deasserts to indicate that the peripheral can accept data. it indicates whether the data lines contain ecp command information or data in the reverse direction. when in reverse direction, normal data are transferred when busy (periphack) is high and an 8-bit command is transferred when it is low. perror (nackreverse) i this signal is used to acknowledge a change in the direction of the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select (xflag) i indicates printer on line. nautofd (hostack) o requests a byte of data from the peripheral when it is asserted. this signal indicates whether the data lines contain ecp address or data in the forward direction. when in forward direction, normal data are transferred when nautofd (hostack) is high and an 8-bit command is transferred when it is low. nfault (nperiphrequest) i generates an error interrupt when it is asserted. this signal is valid only in the forward direction. the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ecp mode. ninit (nreverserequest) o this signal sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the channel in the reverse direction. nselectin (ecpmode) o this signal is always deasserted in ecp mode.
73 ecp operation the host must negotiate on the parallel port to determine if the peripheral supports the ecp protocol before ecp operation. after negotiation, it is necessary to initialize some of the port bits. the following are required: (a) set direction = 0, enabling the drivers. (b) set strobe = 0, causing the nstrobe signal to default to the deasserted state. (c) set autofd = 0, causing the nautofd signal to default to the deasserted state. (d) set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo, respectively. mode switching software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (mode 011 or 010). if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can be changed only in mode 001. when in extended forward mode, the software should wait for the fifo to be empty before switching back to mode 000 or 001. in ecp reverse mode the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. command/data ecp mode allows the transfer of normal 8-bit data or 8-bit commands. in the forward direction, normal data are transferred when hostack is high and an 8-bit command is transferred when hostack is low. the most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. in the reverse direction, normal data are transferred when periphack is high and an 8-bit command is transferred when periphack is low. the most significant bit of the command is always zero. data compression the LPC61W492 supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. note that the odd (rle) compression in hardware is not supported. in order to transfer data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. fifo operation the fifo threshold is set in configuration register 5. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode, as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. after a reset, the fifo is disabled. dma transfers dma transfers are always to or from the ecpdfifo, tfifo, or cfifo. the dma uses the standard pc dma services. the ecp requests dma transfers from the host by activating the pdrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and serviceintr is asserted, which will disable the dma. programmed i/o (non-dma) mode the ecp or parallel port fifos can also be operated using interrupt driven programmed i/o. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. the host must set the direction, state, dmaen = 0 and
74 serviceintr = 0 in the programmed i/o transfers. the ecp requests programmed i/o transfers from the host by activating the irq pin. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. extension fdd mode (extfdd) in this mode, the LPC61W492 changes the printer interface pins to fdc input/output pins, allowing the user to install a second floppy disk drive (fdd b) through the db-25 printer connector. after the printer interface is set to extfdd mode, the following occur: (1) pins nmob and ndsb will be forced to inactive state. (2) pins ndskchg , nrdata , nwp , ntrak0 , nindex will be logically ored with pins pd4-pd0 to serve as input signals to the fdc. (3) pins pd4-pd0 each will have an internal resistor of about 1k ohm to serve as pull-up resistor for fdd open drain/collector output. (4) if the parallel port is set to extfdd mode after the system has booted dos or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. extension 2fdd mode (ext2fdd) in this mode, the LPC61W492 changes the printer interface pins to fdc input/output pins, allowing the user to install two external floppy disk drives through the db-25 printer connector to replace internal floppy disk drives a and b. the pin assignments for the fdc input/output pins are shown in table6-1. after the printer interface is set to extfdd mode, the following occur: (1) pins nmoa , ndsa , nmob , and ndsb will be forced to inactive state. (2) pins ndskchg , nrdata , nwp , ntrak0 , and nindex will be logically ored with pins pd4-pd0 to serve as input signals to the fdc. (3) pins pd4-pd0 each will have an internal resistor of about 1k ohm to serve as pull-up resistor for fdd open drain/collector output. (4) if the parallel port is set to ext2fdd mode after the system has booted dos or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
75 keyboard controller the kbc (8042 with licensed kb bios) circuit of LPC61W492 is designed to provide the functions needed to interface a cpu with a keyboard and/or a ps/2 mouse, and can be used with ibm ) - compatible personal computers or ps/2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. then, the controller will asserts an interrupt to the system when data are placed in its output buffer. the keyboard and ps/2 mouse are required to acknowledge all data transmissions. no transmission should be sent to the keyboard or ps/2 mouse until an acknowledge is received for the previous data byte. 8042 p24 p25 p21 p20 p27 p10 p26 t0 p23 t1 p22 p11 kirq mirq gatea20 kbrst p17 kinh gp i/o pins p12~p16 kdat kclk mclk mdat multiplex i/o pins keyboard and mouse interface
76 output buffer the output buffer is an 8-bit read-only register at i/o address 60h (default, pnp programmable i/o address ld5-cr60 and ld5-cr61). the keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. the output buffer can only be read when the output buffer full bit in the register is "1". input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h (default, pnp programmable i/o address ld5-cr60, ld5-cr61, ld5-cr62, and ld5-cr63). writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register the status register is an 8-bit read-only register at i/o address 64h (default, pnp programmable i/o address ld5-cr62 and ld5-cr63), that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. it defaults to 0 after a power-on reset. 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 auxiliary device output buffer 0: auxiliary device output buffer empty 1: auxiliary device output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error)
77 commands command function 20h read command byte of keyboard controller 60h write command byte of keyboard controller bit 1 2 3 4 5 6 7 0 bit definition reserved ibm keyboard translate mode disable auxiliary device disable keyboard reserve system flag enable auxiliary interrupt enable keyboard interrupt a4h test password returns 0fah if password is loaded returns 0f1h if password is not loaded a5h load password load password until a "0" is received from the system a6h enable password enable the checking of keystrokes for a match with the password a7h disable auxiliary device interface a8h enable auxiliary device interface a9h interface test bit 04 03 02 01 00 bit definition no error detected auxiliary device "clock" line is stuck low auxiliary device "clock" line is stuck high auxiliary device "data" line is stuck low auxiliary device "data" line is stuck low
78 commands, continued command function aah self-test returns 055h if self test succeeds abh interface test bit 04 03 02 01 00 bit definition no error detected keyboard "clock" line is stuck low keyboard "clock" line is stuck high keyboard "data" line is stuck low keyboard "data" line is stuck high adh disable keyboard interface aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bits of port1 into status register c2h continuously puts the upper four bits of port1 into status register d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from auxiliary device d4h output next received byte of data from system to auxiliary device e0h reports the status of the test inputs fxh pulse only rc(the reset line) low for 6 ' s if command byte is even
79 hardware gatea20/keyboard reset control logic the kbc implements a hardware control logic to speed-up gatea20 and kbreset. this control logic is controlled by ld5-crf0 as follows: kb control register (logic device 5, cr-f0) bit 7 6 5 4 3 2 1 0 name kclks1 kclks0 reserved reserved reserved p92en hga20 hkbrst kclks1, kclks0 this 2 bits are for the kbc clock rate selection. = 0 0 kbc clock input is 6 mhz = 0 1 kbc clock input is 8 mhz = 1 0 kbc clock input is 12 mhz = 1 1 kbc clock input is 16 mhz p92en (port 92 enable) a "1" on this bit enables port 92 to control gatea20 and kbreset. a "0" on this bit disables port 92 functions. hga20 (hardware gate a20) a "1" on this bit selects hardware gatea20 control logic to control gate a20 signal. a "0" on this bit disables hardware gatea20 control logic function. hkbrst (hardware keyboard reset) a "1" on this bit selects hardware kb reset control logic to control kbreset signal. a "0" on this bit disable hardware kb reset control logic function. when the kbc receives a data follows a "d1" command, the hardware control logic sets or clears gate a20 according to the received data bit 1. similarly, the hardware control logic sets or clears kbreset depending on the received data bit 0. when the kbc receives a "fe" command, the kbreset is pulse low for 6 ' s (min.) with 14 ' s (min.) delay. gatea20 and kbreset are controlled by either the software control or the hardware control logic and they are mutually exclusive. then, gatea20 and kbreset are merged along with port92 when p92en bit is set. port 92 control register (default value = 0x24) bit 7 6 5 4 3 2 1 0 name res. (0) res. (0) res. (1) res. (0) res. (0) res. (1) sga20 plkbrst sga20 (special gate a20 control) a "1" on this bit drives gate a20 signal to high. a "0" on this bit drives gate a20 signal to low. plkbrst (pull-low kbreset) a "1" on this bit causes kbreset to drive low for 6 ' s(min.) with 14 ' s(min.) delay. before issuing another keyboard reset command, the bit must be cleared.
80 general purpose i/o LPC61W492 provides 24 input/output ports that can be individually configured to perform a simple basic i/o function or a pre-defined alternate function. those 24 gp i/o ports are divided into three groups, each group contains 8 ports. the first group is configured through control registers in logical device 7, the second group in logical device 8, and the third group in logical device 9. users can configure each individual port to be an input or output port by programming respective bit in selection register (crf0: 0 = output, 1 = input). invert port value by setting inversion register (crf2: 0 = non- inverse, 1 = inverse). port value is read/written through data register (crf1). in addition, gpio1 is designed to be functional even in power loss condition (vcc or vsb is off). the following table shows the gp i/o port's structure. right after power-on reset, those ports default to perform basic input function except ports in gpio1which maintains its previous settings until a battery loss condition. selection bit 0 = output 1 = input inversion bit 0 = non inverse 1 = inverse basic i/o operations 0 0 basic non-inverting output 0 1 basic inverting output 1 0 basic non-inverting input 1 1 basic inverting input
81 gp i/o port data register register bit assignment gp i/o port bit 0 gp10 bit 1 gp11 bit 2 gp12 bit 3 gp13 gp1 bit 4 gp14 bit 5 gp15 bit 6 gp16 bit 7 gp17 bit 0 gp20 bit 1 gp21 gp2 bit 2 gp22 bit 3 gp23 bit 4 gp24 bit 5 gp25 bit 6 gp26 bit 7 gp27 bit 0 gp30 bit 1 gp31 bit 2 gp32 bit 3 gp33 gp3 bit 4 gp34 bit 5 gp35 bit 6 gp36 bit 7 gp37
82 figure 1 plug and play configuration the LPC61W492 uses compatible pnp protocol to access configuration registers for setting up different types of configurations. in LPC61W492, there are eleven logical devices (from logical device 0 to logical device b with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: fdc (logical device 0), prt (logical device 1), uart1 (logical device 2), uart2 (logical device 3), kbc (logical device 5), cir (consumer ir, logical device 6), gpio1 (logical device 7), gpio2 (logical device 8), gpio3 (logical device 9), acpi ((logical device a), and hardware monitor (logical device b). each logical device has its own configuration registers (above cr30). host can access those registers by writing an appropriate logical device number into logical device select register at cr7. compatible pnp extended function registers in compatible pnp, there are two ways to enter extended function and read or write the configuration registers. hefras (cr26 bit 6) can be used to select one out of these two methods of entering the extended function mode as follows:
83 hefras address and value 0 write 87h to the location 2eh twice 1 write 87h to the location 4eh twice after power-on reset, the value on nrtsa (pin 43) is latched by hefras of cr26. in compatible pnp, a specific value (87h) must be written twice to the extended functions enable register (i/o port address 2eh or 4eh). secondly, an index value (02h, 07h-ffh) must be written to the extended functions index register (i/o port address 2eh or 4eh same as extended functions enable register) to identify which configuration register is to be accessed. the designer can then access the desired configuration register through the extended functions data register (i/o port address 2fh or 4fh). after programming of the configuration register is finished, an additional value (aah) should be written to efers to exit the extended function mode to prevent unintentional access to those configuration registers. the designer can also set bit 5 of cr26 (lockreg) to high to protect the configuration registers against accidental accesses. the configuration registers can be reset to their default or hardware settings only by a cold reset (pin mr = 1). a warm reset will not affect the configuration registers. extended functions enable registers (efers) after a power-on reset, the LPC61W492 enters the default operating mode. before the LPC61W492 enters the extended function mode, a specific value must be programmed into the extended function enable register (efer) so that the extended function register can be accessed. the extended function enable registers are write-only registers. on a pc/at system, their port addresses are 2eh or 4eh (as described in previous section). extended function index registers (efirs), extended function data registers(efdrs) after the extended function mode is entered, the extended function index register (efir) must be loaded with an index value (02h, 07h-feh) to access configuration register 0 (cr0), configuration register 7 (cr07) to configuration register fe (crfe), and so forth through the extended function data register (efdr). the efirs are write-only registers with port address 2eh or 4eh (as described in section 12.2.1) on pc/at systems; the efdrs are read/write registers with port address 2fh or 4fh (as described in section 9.2.1) on pc/at systems. configuration sequence to program LPC61W492 configuration registers, the following configuration sequence must be followed: (1). enter the extended function mode (2). configure the configuration registers (3). exit the extended function mode enter the extended function mode to place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to extended function enable registers(efers, i.e. 2eh or 4eh). configurate the configuration registers the chip selects the logical device and activates the desired logical devices through extended function index register(efir) and extended function data register(efdr). efir is located at the same address as efer, and efdr is located at address (efir+1).
84 first, write the logical device number (i.e.,0x07) to the efir and then write the number of the desired logical device to the efdr. if accessing the chip(global) control registers, this step is not required. secondly, write the address of the desired configuration register within the logical device to the efir and then write (or read) the desired configuration register through efdr. exit the extended function mode to exit the extended function mode, one write of 0xaa to efer is required. once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. software programming example the following example is written in intel 8086 assembly language. it assumes that the efer is located at 2eh, so efir is located at 2eh and efdr is located at 2fh. if hefras (cr26 bit 6) is set, 4eh can be directly replaced by 4eh and 2fh replaced by 4fh. ;----------------------------------------------------------------------------------- ; enter the extended function mode ,interruptible double-write | ;----------------------------------------------------------------------------------- mov dx,2eh mov al,87h out dx,al out dx,al ;----------------------------------------------------------------------------- ; configurate logical device 1, configuration register crf0 | ;----------------------------------------------------------------------------- mov dx,2eh mov al,07h out dx,al ; point to logical device number reg. mov dx,2fh mov al,01h out dx,al ; select logical device 1 ; mov dx,2eh mov al,f0h out dx,al ; select crf0 mov dx,2fh mov al,3ch out dx,al ; update crf0 with value 3ch ;------------------------------------------ ; exit extended function mode | ;------------------------------------------ mov dx,2eh mov al,aah out dx,al
85 acpi registers features LPC61W492 supports both acpi and legacy power managements. the switch logic of the power management block generates an nsmi interrupt in the legacy mode and an npme interrupt in the acpi mode. the new acpi feature routes nsmi / npme logic output either to nsmi or to npme .the nsmi / npme logic routes to nsmi only when both pme_en = 0 and smipme_oe = 1. similarly, the nsmi / npme logic routes to npme only when both pme_en = 1 and smipme_oe = 1. device idle timers device trap timer sleep/wake state machine wak_sts clock control pme smi global stby irqs logic irq events pme_en smipme_oe pme smi / 0 1 smipme_oe
86 hardware monitor general description the LPC61W492 can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. LPC61W492 provides both lpc and i 2 c tm serial bus interface to access hardware. an 8-bit analog-to-digital converter (adc) was built inside LPC61W492. the LPC61W492 can simultaneously monitor 9 analog voltage inputs, 3 fan tachometer inputs, 3 remote temperature, one case-open detection signal. the remote temperature sensing can be performed by thermistors, or 2n3904 npn-type transistors, or directly from intel tm deschutes cpu thermal diode output. also the LPC61W492 provides: 2 pwm (pulse width modulation) outputs for the fan speed control; beep tone output for warning; nsmi (through serial irq) novt, ngpo signals for system protection events. through the application software or bios, the users can read all the monitored parameters of system from time to time. and a pop-up warning can be also activated when the monitored item was out of the proper/preset range. the application software could be smsc's hardware doctor tm , or intel tm ldcm (landesk client management), or other management application software. also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. an optional beep tone could be used as warning signal when the monitored parameters is out of the preset range. additionally, 5 vid inputs are provided to read the vid of cpu (i.e. pentium tm ii) if applicable. this is to provide the vcore a voltage correction automatically. also the LPC61W492 uniquely provides an optional feature: early stage (before bios was loaded) beep warning. this is to detect if the fatal elements present --- vcore a or +3.3v voltage fail, and the system can not be boomed up. access interface the LPC61W492 provides two interfaces for microprocessor to read/write hardware monitor internal registers. lpc interface the first interface uses lpc bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. the other higher bits of these ports is set by LPC61W492 itself. the general decoded address is set to port 295h and port 296h. these two ports are described as following: port 295h: index port. port 296h: data port. the register structure is showed in the following figure.
87 configuration register 40h smi# status/mask registers 41h, 42h, 44h, 45h vid<3:0>/fan divisor register 47h serial bus address 48h monitor value registers 20h~3fh and 60h~7fh (auto-increment) vid<4>/device id 49h temperature 2, 3 serial bus address 4ah control register 4bh~4dh select bank for 50h~5fh reg. 4eh winbond vendor id 4fh bank 0 r-t table value beep control register winbond test register 50h~58h bank 1 temperature 2 control/staus registers 50h~56h bank 2 temperature 3 control/staus registers 50h~56h data register port 6h port 5h index register isa data bus isa address bus bank 4 additional control/staus registers 50h~5ch bank 5 additional limit value & value ram 50h~57h figure 2 - isa interface access diagram
88 i 2 c interface the second interface uses i 2 c serial bus. LPC61W492 hardware monitor has three serial bus address. that is, the first address defined at cr[48h] can read/write all registers excluding bank 1 and bank 2 temperature sensor 2/3 registers. the second address defined at cr[4ah] bit2-0 only read/write temperature sensor 2 registers, and the third address defined at cr[4ah] bit6-4 only can access (read/write) temperature sensor 3 registers. the first serial bus access timing is shown as follow: (a) serial bus write to internal address register followed by the data byte 0 start by master 01011 01 d7 d6 d5 d4 d3 d2 d1 d0 ack by 781d r/w ack by 781d scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by 781d stop by master scl sda (continued) 780 78 0 78 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte (b) serial bus write to internal address register only 0 start by master 01011 01 d7 d6 d5 d4 d3 d2 d1 d0 ack by 781d r/w ack by 781d scl sda 780 78 0 frame 2 internal index register byte frame 1 serial bus address byte stop by master (c) serial bus read from a register with the internal address register prefer to desired location 0 start by master 01011 01 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by 781d scl sda 780 78 0 frame 2 data byte frame 1 serial bus address byte stop by master
89 the serial bus timing of the temperature 2 and 3 are shown as follows: (a) typical 2-byte read from preset pointer location (temp, t os , t hyst ) 0 start by master 01011 01 d7 d1 d0 ack by master r/w ack by 782d scl sda 780 78 frame 2 msb data byte frame 1 serial bus address byte d7 d1 d0 07 stop b y master ... ... ... ack by master ... frame 3 lsb data byte (b) typical pointer set followed by immediate read for 2-byte register (temp, t os , t hyst ) 0 start by master d7 d1 d0 ack by master ack by 782d scl sda 780 78 0 frame 4 msb data byte frame 3 serial bus address byte d7 d1 d0 07 stop b y master ... ... ... no ack by master ... frame 5 lsb data byte 0 start by master 1001a2 a1 a0 r/w ack by 782d scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by 782d frame 2 pointer byte 1001a2a1a0r/w 000000 (c) typical read 1-byte from configuration register with preset pointer 0 start by master d7 d2 ack by 782d scl sda 780 frame 2 data byte frame 1 serial bus address byte d0 7 stop b y master no ack by master 1001a2a1a0r/w d1 d5 d4 d3 d6 8
90 (d) typical pointer set followed by immediate read from configuration register 0 repea start by master d7 d5 d4 ack by 782d scl (cont..) sda (cont..) 780 frame 4 msb data byte frame 3 serial bus address byte d2 d1 d0 7 stop by master no ack by master 0 start by master 1001a2 a1 a0 r/w ack by 782d scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by 782d frame 2 pointer byte 1001a2a1a0r/w ... ... d6 d3 8 78 00000 0 (e) temperature 2/3 configuration register write 0 ack by 782d scl (cont...) sda (cont...) 78 frame 3 configuration data byte 0 start by master 1001a2 a1 a0 r/w ack by 782d scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by 782d frame 2 pointer byte 0 0 d4 d3 d2 d1 0 d0 stop by master 0000000 78
91 (f) temperature 2/3 t os and t hyst write 0 ack by 781d scl (cont...) sda (cont...) 78 frame 3 msb data byte 0 start by master 1001a2 a1 a0 r/w ack by 782d scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by 782d frame 2 pointer byte d6 d5 d4 d3 d2 d1 d7 d0 0 78 d6 d5 d4 d3 d2 d1 d7 d0 ack by 782d stop by master frame 4 lsb data byte 78 0 0 0000
92 analog inputs the maximum input voltage of the analog pin is 4.096v because the 8-bit adc has a 16mv lsb. really, the application of the pc monitoring would most often be connected to power suppliers. the cpu v-core voltage +3.3v, battery and 5vsb voltage can directly connected to these analog inputs. the +12v,-12v and -5v voltage inputs should be reduced a factor with external resistors so as to obtain the input range, as figure 3 shows. pin 100 vcorea vcoreb pin 99 +3.3vin +12vin pin 98 pin 96 pin 97 avcc(+5v) n12vin vbat pin 95 pin 74 r4 r1 v1 n5vin positive input negative input 8-bit adc with 16mv lsb typical thermister connection 10k, 1% r thm vref pin 101 vtin3 vtin2 vtin1 pin 102 pin 103 pin 104 5vsb pin 61 pin 94 positive inputs r3 r5 r6 10k, 25 c **the connections of vtin1 and vtin2 are same as vtin3 r2 r v2 v3 figure 3 monitor over 4.096v voltage: the input voltage +12vin can be expressed as following equation. 12 1 2 12 vi nv r rr *& + the value of r1 and r2 can be selected to 28k ohms and 10k ohms, respectively, when the input voltage v1 is 12v. the node voltage of +12vin can be subject to less than 4.096v for the maximun input range of the 8-bit adc. the pin 97 is connected to the power supply vcc with +5v. there are two functions in this pin with 5v. the first function is to supply internal analog power in the LPC61W492 and the second function is that this voltage with 5v is connected to internal serial resistors to monitor the +5v voltage. the value of two serial resistors are 34k ohms and 50k ohms so that input voltage to adc is 2.98v which is less than 4.096v of adc maximum input voltage. the express equation can represent as follows.
93 vvcc k kk v i n *& + , 50 50 34 298 " "" . where vcc is set to 5v. the pin 61 is connected to 5vsb voltage. LPC61W492 monitors this voltage and the internal two serial resistors are 17k " and 33k " so that input voltage to adc is 3.3v which less than 4.096v of adc maximum input voltage. monitor negative voltage: the negative voltage should be connected two series resistors and a positive voltage vref (is equal to 3.6v). in figure 3, the voltage v2 and v3 are two negative voltage which they are -12v and -5v respectively. the voltage v2 is connected to two serial resistors then is connected to another terminal vref which is positive voltage. so as that the voltage node n12vin can be obtain a posedge voltage if the scales of the two serial resirtors are carefully selected. it is recommanded from smsc that the scale of two serial resistors are r3=232k ohms and r4=56k ohm. the input voltage of node n12vin can be calculated by following equation. n vin vref v k kk v 12 232 232 56 22 *+& + + ()( ) " "" where vref is equal 3.6v. if the v2 is equal to -12v then the voltage is equal to 0.567v and the converted hexdecimal data is set to 35h by the 8-bit adc with 16mv-lsb.this monitored value should be converted to the real negative votage and the express equation is shown as follows. v n vin vref 2 12 1 * !& ! - - where - is 232k/(232k+56k). if the n2vin is 0.567 then the v2 is approximately equal to -12v. the another negative voltage input v3 (approximate -5v) also can be evaluated by the similar method and the serial resistors can be selected with r5=120k ohms and r6=56k ohms by the smsc recommended. the expression equation of v3 with -5v voltage is shown as follows. v n vin vref 3 5 1 * !& ! . . where the . is set to 120k/(120k+56k). if the monitored adc value in the n5vin channel is 0.8635, vref=3.6v and the parameter . is 0.6818 then the negative voltage of v3 can be evalated to be -5v.
94 temperature measurement machine the temperature data format is 8-bit two's-complement for sensor 2 and 9-bit two's-complement for sensor 1. the 8-bit temperature data can be obtained by reading the cr[27h]. the 9-bit temperature data can be obtained by reading the 8 msbs from the bank1 cr[50h] and the lsb from the bank1 cr[51h] bit 7. temperature 8-bit digital output 9-bit digital output 8-bit binary 8-bit hex 9-bit binary 9-bit hex +125 c 0111,1101 7dh 0,1111,1010 0fah +25 c 0001,1001 19h 0,0011,0010 032h +1 c 0000,0001 01h 0,0000,0010 002h +0.5 c - - 0,0000,0001 001h +0 c 0000,0000 00h 0,0000,0000 000h -0.5 c - - 1,1111,1111 1ffh -1 c 1111,1111 ffh 1,1111,1110 1ffh -25 c 1110,0111 e7h 1,1100,1110 1ceh -55 c 1100,1001 c9h 1,1001,0010 192h monitor temperature from thermistor: the LPC61W492 can connect three thermistors to measure three different envirment temperature. the specification of thermistor should be considered to (1) - value is 3435k, (2) resistor value is 10k ohms at 25 / c. in figure 4, the themistor is connected by a serial resistor with 10k ohms, then connect to vref (pin 101). monitor temperature from pentium ii tm thermal diode or bipolar transistor 2n3904 the LPC61W492 can alternate the thermistor to pentium ii tm (deschutes) thermal diode interface or transistor 2n3904 and the circuit connection is shown as figure 11.3. the pin of pentium ii tm d- is connected to power supply ground (gnd) and the pin d+ is connected to pin vtinx in the LPC61W492. the resistor r=30k ohms should be connected to vref to supply the diode bias current and the bypass capacitor c=3300pf should be added to filter the high frequency noise. the transistor 2n3904 should be connected to a form with a diode, that is, the base (b) and collector (c) in the 2n3904 should be tied togeter to act as a thermal diode.
95 2n3904 c e b r=30k, 1% c=3300pf bipolar transistor temperature sensor pentium ii cpu d+ d- therminal diode c=3300pf r=30k, 1% vref vtinx vtinx or w83627hf figure - 3 fan speed count and fan speed control fan speed count inputs are provides for signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage can not be over +5.5v. if the input signals from the tachometer outputs are over the vcc, the external trimming circuit should be added to reduce the voltage to obtain the input specification. the normal circuit and trimming circuits are shown as figure 4. determine the fan counter according to: count rpm divisor * & & 135 10 6 . in other words, the fan speed counter has been read from register cr28 or cr29 or cr2a, the fan speed can be evaluated by the following equation. rpm c ount d i vi so r * & & 135 10 6 . the default divisor is 2 and defined at cr47.bit7~4, cr4b.bit7~6, and bank0 cr5d.bit5~7 which are three bits for divisor. that provides very low speed fan counter such as power supply fan. the followed table is an example for the relation of divisor, prm, and count.
96 divisor nominal prm time per revolution counts 70% rpm time for 70% 1 8800 6.82 ms 153 6160 9.74 ms 2 (default) 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms fan connector fan out +12v gnd pull-up resister 4.7k ohms +5v +12v fan input pin 111-113 w83627hf fan connector fan out +12v gnd pull-up resister 4.7k ohms +12v fan input pin 111-113 w83627hf 14k~39k 10k fan with tach pull-up to +12v, or totem-pole output and register attenuator fan with tach pull-up to +5v fan connector fan out +12v gnd pull-up resister > 1k +12v fan input pin 111-113 w83627hf fan connector fan out +12v gnd pull-up resister < 1k or totem-pole output +12v fan input pin 111-113 w83627hf > 1k fan with tach pull-up to +12v, or totem-pol e output and zener clamp fan with tach pull-up to +12v and zener cla m 3.9v zener 3.9v zener diode diode diode diode figure - 4
97 fan speed control the LPC61W492 provides 2 sets for fan pwm speed control. the duty cycle of pwm can be programmed by a 8-bit registers which are defined in the bank0 cr5a and cr5b. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. dut ycycl e program m ed 8-bi t regi st er val ue 255 !* & ( % ) 100% the pwm clock frequency also can be program and defined in the bank0.cr5c. the application circuit is shown as follows. +12v fan r1 r2 nmos pnp transist c + - pwm clock input d s g figure - 5
98 nsmi interrupt mode voltage nsmi mode: nsmi interrupt for voltage is two-times interrupt mode. voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt status register. (figure 6) fan nsmi mode: nsmi interrupt for fan is two-times interrupt mode. fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt status register. (figure 7) *** *interrupt reset when interrupt status registers are read smi# * high limit low limit * smi# * fan count limit figure - 6 figure - 7
99 the LPC61W492 temperature sensor 1 nsmi interrupt has two modes: (1) comparator interrupt mode setting the t hyst (temperature hysteresis) limit to 127 c will set temperature sensor 1 nsmi to the comparator interrupt mode. temperature exceeds t o (over temperature) limit causes an interrupt and this interrupt will be reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t o , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t o . (figure 8) (2) two-times interrupt mode setting the t hyst lower than t o will set temperature sensor 1 nsmi to the two-times interrupt mode. temperature exceeding t o causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 9) t oi t hyst ** *interrupt reset when interrupt status registers are read t oi t hyst smi# smi# ** * * * 127'c figure - 8 figure - 9
100 the LPC61W492 temperature sensor 2 and sensor 3 nsmi interrupt has two modes and it is programmed at cr[4ch] bit 6. (1) comparator interrupt mode temperature exceeding t o causes an interrupt and this interrupt will be reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t hyst . (figure 10) (2) two-times interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 11) t oi t hyst *** *interrupt reset when interrupt status registers are read t oi t hyst smi# smi# ** * * * figure - 10 figure - 11
101 novt interrupt mode the novt signal is only related with temperature sensor 2 and 3 (vtin2 / vtin3). the LPC61W492 temperature sensor 2 and 3 over-temperature (novt) has the following modes (1) comparator mode: setting bank1/2 cr[52h] bit 2 to 0 will set novt signal to comparator mode. temperature exceeding t o causes the novt output activated until the temperature is less than t hyst . (figure 12) (2) interrupt mode: setting bank1/2 cr[52h] bit 2 to 1 will set novt signal to interrupt mode. setting temperature exceeding t o causes the novt output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. temperature exceeding t o , then novt reset, and then temperature going below t hyst will also cause the novt activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. once the novt is activated by exceeding t o , then reset, if the temperature remains above t hyst , the novt will not be activated again. (figure 12) t hyst *** *interru p t reset when tem p erature 2/3 is read ovt# ovt# * (comparator mode; default) (interrupt mode) to figure ? 12
102 registers and ram address register (port x5h) data port: port x5h power on default value 00h attribute: bit 6:0 read/write , bit 7: read only size: 8 bits 7 6 5 4 3 2 1 0 data bit7: read only the logical 1 indicates the device is busy because of a serial bus transaction or another lpc bus transaction. with checking this bit, multiple lpc drivers can use LPC61W492 hardware monitor without interfering with each other or a serial bus driver. it is the user's responsibility not to have a serial bus and lpc bus operations at the same time. this bit is: set: with a write to port x5h or when a serial bus transaction is in progress. reset: with a write or read from port x6h if it is set by a write to port x5h, or when the serial bus transaction is finished. bit 6-0: read/write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 busy address pointer (power on default 00h) (power on default 0) a6 a5 a4 a3 a2 a1 a0
103 address pointer index (a6-a0) registers and ram a6-a0 in hex power on value of registers: in binary notes configuration register 40h 00001000 interrupt status register 1 41h 00000000 auto-increment to the address of interrupt status register 2 after a read or write to port x6h. interrupt status register 2 42h 00000000 nsmiy mask register 1 43h 00000000 auto-increment to the address of smiy mask register 2 after a read or write to port x6h. smiy mask register 2 44h 00000000 nmi mask register 1 45h 00000000 auto-increment to the address of nmi mask register 2 after a read or write to port x6h nmi mask register 2 46h 01000000 vid/fan divisor register 47h <7:4> = 0101; <3:0> = vid3-vid0 serial bus address register 48h <7> = 0 ; <6:0> = 0101101 vid4 & device id register 49h <7:1> = 0000001; <0> = vid4 temperature 2 and temperature 3 serial bus address register 4ah <7:0> = 00000001 pin control register 4bh <7:0> = 01000100 irq/novt property select register 4ch <7:0> = 00000000 fan in/out and beep control register 4dh <7:0> = 00010101 register 50h-5fh bank select register 4eh <7> = 1 ; <6:3> = reserved ; <2:0> = 000 smsc vendor id register 4fh <7:0> = 01011100 (high byte) <7:0> = 10100011 (low byte)
104 address pointer index (a6-a0). continued registers and ram a6-a0 in hex power on value of registers: in binary notes post ram 00-1fh auto-increment to the next location after a read or write to port x6h and stop at 1fh. value ram 20-3fh value ram 60-7fh auto-increment to the next location after a read or write to port x6h and stop at 7fh. temperature 2 registers bank1 50h-56h temperature 3 registers bank2 50h-56h additional configuration registers bank4 50h-5dh value ram bank5 50-57h
105 data register (port x6h) data port: port x6h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 data bit 7-0: data to be read from or to be written to ram and register. configuration register 0 0 0 0 index 40h register location: 40h power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 start smi#enable reserved int_clear reserved reserved reserved initialization bit 7: a one restores power on default value to all registers except the serial bus address register. this bit clears itself since the power on default is zero. bit 6: reserced bit 5: reserved bit 4: reserved bit 3: a one disables the nsmi output without affecting the contents of interrupt status registers. the device will stop monitoring. it will resume upon clearing of this bit. bit 2: reserved bit 1: a one enables the nsmi interrupt output. bit 0: a one enables startup of monitoring operations, a zero puts the part in standby mode. note: the outputs of interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "int_clear'' bit.
106 interrupt status register 1 0 0 0 0 index 41h register location: 41h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcorea vcoreb +3.3vin +5vin temp1 temp2 fan1 fan2 bit 7: a one indicates the fan count limit of fan2 has been exceeded. bit 6: a one indicates the fan count limit of fan1 has been exceeded. bit 5: a one indicates a high limit of vtin2 has been exceeded from temperature sensor 2. bit 4: a one indicates a high limit of vtin1 has been exceeded from temperature sensor 1. bit 3: a one indicates a high or low limit of +5vin has been exceeded. bit 2: a one indicates a high or low limit of +3.3vin has been exceeded. bit 1: a one indicates a high or low limit of vcoreb has been exceeded. bit 0: a one indicates a high or low limit of vcorea has been exceeded.
107 interrupt status register 2 0 0 0 0 index 42h register location: 42h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 +12vin -12vin -5vin fan3 chassis intrusion temp3 reserved reserved bit 7-6:reserved.this bit should be set to 0. bit 5: a one indicates a high limit of vtin3 has been exceeded from temperature sensor 3. bit 4: a one indicates chassis intrusion has gone high. bit 3: a one indicates the fan count limit of fan3 has been exceeded. bit 2: a one indicates a high or low limit of -5vin has been exceeded. bit1: a one indicates a high or low limit of -12vin has been exceeded. bit0: a one indicates a high or low limit of +12vin has been exceeded. nsmi mask register 1 0 0 0 0 index 43h register location: 43h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vcorea vcoreb +3.3vin +5vin temp1 temp2 fan1 fan2 bit 7-0: a one disables the corresponding interrupt status bit for nsmi interrupt.
108 nsmi mask register 2 0 0 0 0 index 44h register location: 44h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 +12vin -12vin -5vin fan3 chassis intrusion temp3 reserved reserved bit 7-6: reserved. this bit should be set to 0. bit 5-0: a one disables the corresponding interrupt status bit for nsmi interrupt. reserved register 0 0 0 0 index 45h chassis clear register -- index 46h register location: 46h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved chassis clear bit 7: set 1, clear chassis intrusion event. this bit self clears after clearing chassis intrusion event. bit 6-0:reserved. this bit should be set to 0.
109 vid/fan divisor register 0 0 0 0 index 47h register location: 47h power on default value <7:4> is 0101, <3:0> is mapped to vid<3:0> attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vid0 vid1 vid2 vid3 fan1div_b0 fan1div_b1 fan2div_b0 fan2div_b1 bit 7-6: fan2 speed control. bit 5-4: fan1 speed control. bit 3-0: the vid <3:0> inputs note : please refer to bank0 cr[5dh] , fan divisor table. serial bus address register 0 0 0 0 index 48h register location: 48h power on default value serial bus address 2dh size: 8 bits 7 6 5 4 3 2 1 0 serial bus address reserved bit 7: read only - reserved. bit 6-0: read/write - serial bus address <6:0>.
110 value ram 0 0 0 0 index 20h- 3fh or 60h - 7fh (auto-increment) address a6-a0 address a6-a0 with auto- increment description 20h 60h vcorea reading 21h 61h vcoreb reading 22h 62h +3.3vin reading 23h 63h +5vin reading 24h 64h +12vin reading 25h 65h -12vin reading 26h 66h -5vin reading 27h 67h temperature reading 28h 68h fan1 reading note: this location stores the number of counts of the internal clock per revolution. 29h 69h fan2 reading note: this location stores the number of counts of the internal clock per revolution. 2ah 6ah fan3 reading note: this location stores the number of counts of the internal clock per revolution. 2bh 6bh vcorea high limit, default value is defined by vcore voltage +0.2v. 2ch 6ch vcorea low limit, default value is defined by vcore voltage -0.2v. 2dh 6dh vcoreb high limit. 2eh 6eh vcoreb low limit. 2fh 6fh +3.3vin high limit 30h 70h +3.3vin low limit 31h 71h +5vin high limit 32h 72h +5vin low limit 33h 73h +12vin high limit 34h 74h +12vin low limit 35h 75h -12vin high limit 36h 76h -12vin low limit
111 value ram 0 0 0 0 index 20h- 3fh or 60h - 7fh (auto-increment), continued address a6-a0 address a6-a0 with auto- increment description 37h 77h -5vin high limit 38h 78h -5vin low limit 39h 79h temperature sensor 1 (vtin1) high limit 3ah 7ah temperature sensor 1 (vtin1) hysteresis limit 3bh 7bh fan1 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3ch 7ch fan2 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3dh 7dh fan3 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3e- 3fh 7e- 7fh reserved setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. voltage id (vid4) & device id register - index 49h register location: 49h power on default value <7:1> is 000,0001 binary <0> is mapped to vid <4> size: 8 bits 7 6 5 4 3 2 1 0 did<6:0> vid4 bit 7-1: read only - device id<6:0> bit 0 : read/write - the vid4 inputs.
112 temperature 2 and temperature 3 serial bus address register--index 4ah register location: 4ah power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 i2caddr2 i2caddr2 i2caddr2 dis_t2 i2caddr3 i2caddr3 i2caddr3 dis_t3 bit 7: set to 1, disable temperature sensor 3 and can not access any data from temperature sensor 3. bit 6-4: temperature 3 serial bus address. the serial bus address is 1001 xxx. where xxx are defi ned in these bits. bit 3: set to 1, disable temperature sensor 2 and can not access any data from temperature sensor 2. bit 2-0: temperature 2 serial bus address. the serial bus address is 1001 xxx. where xxx are defi ned in these bits. pin control register - index 4bh register location: 4bh power on default value 44h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved clkinsel clkinsel adcovsel adcovsel fan3div_b0 fan3div_b1 bit 7-6:fan3 speed divisor. please refer to bank0 cr[5dh] , fan divisor table. bit 5-4: select a/d converter clock input. <5:4> = 00 - default. adc clock select 22.5 khz. <5:4> = 01- adc clock select 5.6 khz. (22.5k/4) <5:4> = 10 - adc clock select 1.4khz. (22.5k/16) <5:4> = 11 - adc clock select 0.35 khz. (22.5k/64) bit 3-2: clock input select.
113 <3:2> = 00 - pin 3 (clkin) select 14.318mhz clock. <3:2> = 01 - default. pin 3 (clkin) select 24mhz clock. <3:2> = 10 - pin 3 (clkin) select 48mhz clock . <3:2> = 11 - reserved. pin3 no clock input. bit 1-0: reserved. user defined. irq/novt property select register- index 4ch register location: 4ch power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved ovtpol dis_ovt1 dis_ovt2 reserved t23_intmode reserved bit 7: reserved. user defined. bit6: set to 1, the nsmi output type of temperature 2 and 3 is set to comparator interrupt mode. set to 0, the nsmi output type is set to two-times interrupt mode. (default 0) bit5: reserved. user defined. bit 4: disable temperature sensor 3 over-temperature (ovt) output if set to 1. default 0, enable ovt2 output through pin novt. bit 3: disable temperature sensor 2 over-temperature (ovt) output if set to 1. default 0, enable ovt1 output through pin novt. bit 2: over-temperature polarity. write 1, novt active high. write 0, novt active low. default 0. bit 1: reserved. bit 0: reserved.
114 fan in/out and beep control register- index 4dh register location: 4dh power on default value 15h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 faninc1 fanopv1 faninc2 fanopv2 faninc3 fanopv3 reserved dis_abn bit 7: disable power-on abnormal the monitor voltage including v-core a and +3.3v. if these voltage exceed the limit value, the pin (open drain) of beep will drives 300hz and 600hz frequency signal. write 1, the frequency will be disable. default 0. after power on, the system should set 1 to this bit to 1 in order to disable beep. bit 6: reserved. bit 5: fan 3 output value if faninc3 sets to 0. write 1, then pin 18 always generate logic high signal. write 0, pin 18 always generates logic low signal. this bit default 0. bit 4: fan 3 input control. set to 1, pin 18 acts as fan clock input, which is default value. set to 0, this pin 18 acts as fan control signal and the output value of fan control is set by this register bit 5. bit 3: fan 2 output value if faninc2 sets to 0. write 1, then pin 19 always generate logic high signal. write 0, pin 19 always generates logic low signal. this bit default 0. bit 2: fan 2 input control. set to 1, pin 19 acts as fan clock input, which is default value. set to 0, this pin 19 acts as fan control signal and the output value of fan control is set by this register bit 3. bit 1: fan 1 output value if faninc1 sets to 0. write 1, then pin 20 always generate logic high signal. write 0, pin 20 always generates logic low signal. this bit default 0. bit 0: fan 1 input control. set to 1, pin 20 acts as fan clock input, which is default value. set to 0, this pin 20 acts as fan control signal and the output value of fan control is set by this register bit 1.
115 register 50h ~ 5fh bank select register - index 4eh (no auto increase) register location: 4eh power on default value 80h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 banksel0 banksel1 banksel2 reserved reserved reserved reserved hbacs bit 7: hbacs- high byte access. set to 1, access register 4fh high byte register. set to 0, access register 4fh low byte register. default 1. bit 6-3: reserved. this bit should be set to 0. bit 2-0: index ports 0x50~0x5f bank select. smsc vendor id register - index 4fh (no auto increase) register location: 4fh power on default value <15:0> = 5ca3h attribute: read only size: 16 bits 15 8 7 0 vidh vidl bit 15-8: vendor id high byte if cr4e.bit7=1.default 5ch. bit 7-0: vendor id low byte if cr4e.bit7=0. default a3h.
116 smsc test register -- index 50h - 55h (bank 0) beep control register 1-- index 56h ( bank 0 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vca_bp en_vcb_bp en_v33_bp en_v5_bp en_t1_bp en_t2_bp en_fan1_bp en_fan2_bp bit 7: enable beep output from fan 2 if the monitor value exceed the limit value. write 1, enable beep output, which is default value. bit 6: enable beep output from fan 1 if the monitor value exceed the limit value. write 1, enable beep output, which is default value. bit 5: enable beep output from temperature sensor 2 if the monitor value exceed the limit value. write 1, enable beep output. default 0 bit 4: enable beep output for temperature sensor 1 if the monitor value exceed the limit value. write 1, enable beep output. default 0 bit 3: enable beep output from vdd (+5v), write 1, enable beep output if the monitor value exceed the limits value. default 0, that is disable beep output. bit 2: enable beep output from +3.3v. write 1, enable beep output, which is default value. bit 1: enable beep output from vcoreb. write 1, enable beep output, which is default value. bit 0: enable beep output from vcorea if the monitor value exceed the limits value. write 1, enable beep output, which is default value
117 beep control register 2-- index 57h ( bank 0 ) register location: 57h power on default value 80h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_v12_bp en_nv12_bp en_nv5_bp en_fan3_bp en_caso_bp en_t3_bp reserved en_gbp bit 7: enable global beep. write 1, enable global beep output. default 1. write 0, disable all beep output. bit 6: reserved. this bit should be set to 0. bit5: enable beep output from temperature sensor 3 if the monitor value exceed the limit value. write 1, enable beep output. default 0 bit 4: enable beep output for case open if the monitor value exceed the limit value. write 1, enable beep output. default 0. bit 3: enable beep output from fan 3 if the monitor value exceed the limit value. write 1, enable beep output. default 0. bit 2: enable beep output from -5v, write 1, enable beep output if the monitor value exceed the limits value. default 0, that is disable beep output. bit 1: enable beep output from -12v, write 1, enable beep output if the monitor value exceed the limits value. default 0, that is disable beep output. bit 0: enable beep output from +12v, write 1, enable beep output if the monitor value exceed the limits value. default 0, that is disable beep output.
118 chip id -- index 58h ( bank 0 ) register location: 58h power on default value 21h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 chipid bit 7: smsc chip id number. read this register will return 21h. reserved register -- index 59h ( bank 0 ) pwmout1 control -- index 5ah ( bank 0 ) register location: 5ah power on default value: ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm1_duty bit 7: pwmout1 duty cycle control write ff, duty cycle is 100%, write 00, duty cycle is 0%.
119 pwmout2 control -- index 5bh ( bank 0 ) register location: 5bh power on default value: ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm2_duty bit 7: pwmout2 duty cycle control write ff, duty cycle is 100%, write 00, duty cycle is 0%. pwmout1/2 clock select -- index 5ch ( bank 0 ) register location: 5ch power on default value 11h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm1clksel pwm1clksel pwm1clksel reserved pwm2clksel pwm2clksel pwm2clksel reserved bit 7: reserved bit 6-4: pwmout2 clock selection. the clock defined frequency is same as pwmout1 clock selection. bit 3: reserved bit 2-0: pwmout1 clock selection. <2:0> = 000: 46.87khz <2:0> = 001: 23.43khz (default) <2:0> = 010: 11.72khz <2:0> = 011: 5.85khz <2:0> = 100: 2.93khz
120 vbat monitor control register -- index 5dh ( bank 0 ) register location: 5dh power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vbat_mnt reserved reserved reserved reserved fandiv1_b2 fandiv2_b2 fandiv3_b2 bit 7: fan3 divisor bit 2. bit 6: fan2 divisor bit 2. bit 5: fan1 divisor bit 2. bit 4: reserved. bit 3: reserved. bit 2: reserved. bit 1: reserved. bit 0: set to 1, enable battery voltage monitor. set to 0, disable battery voltage monitor. if enabled this bit, the monitor value is value after one monitor cycle. note that the monitor cycle time is at least 300ms for LPC61W492 hardware monitor. fan divisor table bit 2 bit 1 bit 0 fan divisor bit 2 bit 1 bit 0 fan divisor 0 0 0 1 1 0 0 16 0 0 1 2 1 0 1 32 0 1 0 4 1 1 0 64 0 1 1 8 1 1 1 128 reserved register -- 5eh ( bank 0 ) reserved register -- index 5fh ( bank 0 )
121 temperature sensor 2 temperature (high byte) register - index 50h ( bank 1 ) register location: 50h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<8:1> bit 7: temperature <8:1> of sensor 2, which is high byte. temperature sensor 2 temperature (low byte) register - index 51h ( bank 1 ) register location: 51h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<0> reserved bit 7: temperature <0> of sensor2, which is low byte. bit 6-0: reserved.
122 temperature sensor 2 configuration register - index 52h ( bank 1 ) register location: 52h power on default value 00h size: 8 bits 7 6 5 4 3 2 1 0 stop2 intmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting novt output to avoid false tripping due to noise. bit 2: read - reserved. this bit should be set to 0. bit 1: read/write - novt interrupt mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitor. temperature sensor 2 hysteresis (high byte) register - index 53h ( bank 1 ) register location: 53h power on default value 4bh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst2<8:1> bit 7-0: temperature hysteresis bit 8-1, which is high byte. the temperature default 75 degree c.
123 temperature sensor 2 hysteresis (low byte) register - index 54h ( bank 1 ) register location: 54h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst2<0> reserved bit 7: hysteresis temperature bit 0, which is low byte. bit 6-0: reserved. temperature sensor 2 over-temperature (high byte) register - index 55h ( bank 1 ) register location: 55h power on default value 50h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf2<8:1> bit 7-0: over-temperature bit 8-1, which is high byte. the temperature default 80 degree c.
124 temperature sensor 2 over-temperature (low byte) register - index 56h ( bank 1 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf2<0> reserved bit 7: over-temperature bit 0, which is low byte. bit 6-0: reserved. temperature sensor 3 temperature (high byte) register - index 50h ( bank 2 ) register location: 50h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<8:1> bit 7-0: temperature <8:1> of sensor 2, which is high byte.
125 temperature sensor 3 temperature (low byte) register - index 51h ( bank 2 ) register location: 51h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<0> reserved bit 7: temperature <0> of sensor2, which is low byte. bit 6-0: reserved. temperature sensor 3 configuration register - index 52h ( bank 2 ) register location: 52h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 stop3 intmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting novt output to avoid false tripping due to noise. bit 2: read - reserved. this bit should be set to 0. bit 1: read/write - novt interrupt mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitor.
126 temperature sensor 3 hysteresis (high byte) register - index 53h ( bank 2 ) register location: 53h power on default value 4bh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst3<8:1> bit 7-0: temperature hysteresis bit 8-1, which is high byte. the temperature default 75 degree c. temperature sensor 3 hysteresis (low byte) register - index 54h ( bank 2 ) register location: 54h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst3<0> reserved bit 7: hysteresis temperature bit 0, which is low byte. bit 6-0: reserved.
127 temperature sensor 3 over-temperature (high byte) register - index 55h ( bank 2 ) register location: 55h power on default value 50h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf3<8:1> bit 7-0: over-temperature bit 8-1, which is high byte. the temperature default 80 degree c. temperature sensor 3 over-temperature (low byte) register - index 56h( bank 2 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf3<0> reserved bit 7: over-temperature bit 0, which is low byte. bit 6-0: reserved.
128 interrupt status register 3 -- index 50h (bank4) register location: 50h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 5vsb vbat reserved reserved reserved reserved reserved reserved bit 7-2: reserved. bit 1: a one indicates a high or low limit of vbat has been exceeded. bit 0: a one indicates a high or low limit of 5vsb has been exceeded. nsmi mask register 3 -- index 51h (bank 4) register location: 51h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 5vsb vbat reserved reserved reserved reserved reserved reserved bit 7-2: reserved. bit 1: a one disables the corresponding interrupt status bit for nsmi interrupt. bit 0: a one disables the corresponding interrupt status bit for nsmi interrupt.
129 reserved register -- index 52h ( bank 4 ) beep control register 3-- index 53h ( bank 4 ) register location: 53h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_5vsb_bp en_vbat_bp reserved reserved reserved en_user_bp reserved reserved bit 7-6: reserved. bit 5: user defined beep output function. write 1, the beep is always active. write 0, this function is inactive. (default 0) bit 4-2: reserved. bit 1: enable beep output from vbat. write 1, enable beep output, which is default value. bit 0: enable beep output from 5vsb. write 1, enable beep output, which is default value. temperature sensor 1 offset register -- index 54h ( bank 4 ) register location: 54h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 offset1<7:0> bit 7-0: temperature 1 base temperature. the temperature is added by both monitor value and offset value.
130 temperature sensor 2 offset register -- index 55h ( bank 4 ) register location: 55h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 offset2<7:0> bit 7-0: temperature 2 base temperature. the temperature is added by both monitor value and offset value. temperature sensor 3 offset register -- index 56h ( bank 4 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 offset3<7:0> bit 7-0: temperature 3 base temperature. the temperature is added by both monitor value and offset value. reserved register -- index 57h--58h
131 real time hardware status register i -- index 59h ( bank 4 ) register location: 59h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcorea_sts vcoreb_sts +3.3vin_sts +5vin_sts temp1_sts temp2_sts fan1_sts fan2_sts bit 7: fan 2 status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is in the limit range. bit 6: fan 1 status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is in the limit range. bit 5: temperature sensor 2 status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. bit 4: temperature sensor 1 status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. bit 3: +5v voltage status. set 1, the voltage of +5v is over the limit value. set 0, the voltage of +5v is in the limit range. bit 2: +3.3v voltage status. set 1, the voltage of +3.3v is over the limit value. set 0, the voltage of +3.3v is in the limit range. bit 1: vcoreb voltage status. set 1, the voltage of vcoreb is over the limit value. set 0, the voltage of vcoreb is in the limit range. bit 0: vcorea voltage status. set 1, the voltage of vcore a is over the limit value. set 0, the voltage of vcore a is in the limit range.
132 real time hardware status register ii -- index 5ah ( bank 4 ) register location: 5ah power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 +12vin_sts -12vin_sts -5vin_sts fan3_sts case_sts temp3_sts reserved reserved bit 7-6: reserved bit 5: temperature sensor 3 status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. bit 4: case open status. set 1, the case open sensor is sensed the high value. set 0 bit 3: fan3 voltage status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is during the limit range. bit 2: -5v voltage status. set 1, the voltage of -5v is over the limit value. set 0, the voltage of -5v is during the limit range. bit 1: -12v voltage status. set 1, the voltage of -12v is over the limit value. set 0, the voltage of -12v is during the limit range. bit 0: +12v voltage status. set 1, the voltage of +12v is over the limit value. set 0, the voltage of+12v is in the limit range. real time hardware status register iii -- index 5bh ( bank 4 ) register location: 5bh power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 5vsb_sts vbat_sts reserved reserved reserved reserved reserved reserved bit 7-2: reserved. bit 1: vbat voltage status. set 1, the voltage of vbat is over the limit value. set 0, the voltage of vbat is during the limit range. bit 0: 5vsb voltage status. set 1, the voltage of 5vsb is over the limit value. set 0, the voltage of 5vsb is in the limit range.
133 reserved register -- index 5ch-5dh ( bank 4 ) value ram 2 0 0 0 0 index 50h - 57h (auto-increment) (bank 5) address a6-a0 auto-increment description 50h 5vsb reading 51h vbat reading 52h reserved 53h reserved 54h 5vsb high limit 55h 5vsb low limit. 56h vbat high limit 57h vbat low limit smsc test register -- index 50h ( bank 6 )
134 serial irq LPC61W492 supports a serial irq scheme. this allow a signal line to be used to report the legacy isa interrupt rerquests. because more than one device may need to share the signal serial irq signal line, an open drain signal scheme is used. the clock source is the pci clock. the serial interrupt is transfered on the irqser signal, one cycle consisting of three frames types: a start frame, several irq/data frame, and one stop frame. start frame there are two modes of operation for the irqser start frame: quiet mode and continuous mode. in the quiet mode, the peripheral drives the serirq signal activelow for one clock, and then tri-states it. this brings all the states machines of the peripherals from idle to active states. the host controller will then take over driving irqser signal low in the next clock and will continue driving the irqser low for programmable 3 to 7 clock periods. this makes the total number of clocks low for 4 to 8 clock periods. after these clocks, the host controller will drive the irqser high for one clock and then tri- states it. in the continuous mode, only the host controller initiates the start frame to update irq/data line information. the host controller drives the irqser signal low for 4 to 8 clock periods. upon a reset, the irqser signal is defaulted to the continuous mode for the host controller to initiate the first start frame. irq/data frame once the start frame has been initiated, all the peripherals must start counting frames based on the rsing edge of the start pulse. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase, the peripheral drives serirq low if the corresponding irq is active. if the corresponding irq is inactive, then irqser must be left tri-stated. during the recovery phase, the peripheral device drives the irqser high. during the turn-around phase, the peripheral device left the irqser tri-stated. the irq/data frame has a number of specific order, as shown in the following table.
135 irqser sampling periods irq/data frame signal sampled # of clocks past start 1 irq0 2 2 irq1 5 3 nsmi 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 17 niochck 50 18 ninta 53 19 nintb 56 20 nintc 59 21 nintd 62 32:22 unassigned 95 stop frame after all irq/data frames have completed, the host controller will terminate irqser by a stop frame. only the host controller can initiate the stop frame by driving irqser low for 2 or 3 clocks. if the stop frame is low for 2 clocks, the next irqser cycle's sample mode is the quiet mode. if the stop frame is low for 3 clocks, the next irqser cycle's sample mode is the continuous mode.
136 configuration register chip (global) control register cr02 (default 0x00) bit 7 - 1: reserved. bit 0: swrst --> soft reset. cr07 bit 7 - 0: ldnb7 - ldnb0 --> logical device number bit 7 - 0 cr20 bit 7 - 0: devidb7 - debidb0 --> device id bit 7 - bit 0 = 0x52 (read only). cr21 bit 7 - 0: devrevb7 - debrevb0 --> device rev bit 7 - bit 0 = 0x11 (read only). cr22 (default 0xff) bit 7: reserved. bit 6: hmpwd = 0 power down = 1 no power down bit 5: urbpwd = 0 power down = 1 no power down bit 4: urapwd = 0 power down = 1 no power down bit 3: prtpwd = 0 power down = 1 no power down bit 2, 1: reserved. bit 0: fdcpwd = 0 power down = 1 no power down cr23 (default 0x00) bit 7 - 1: reserved. bit 0: ipd (immediate power down). when set to 1, it will put the whole chip into power down mode immediately. cr24 (default 0b1s000s0s) bit 7: en16sa = 0 12 bit address qualification = 1 16 bit address qualification bit 6: clksel = 0 the clock input on pin 1 should be 24 mhz. = 1 the clock input on pin 1 should be 48 mhz. the corresponding power-on setting pin is soutb (pin 82). bit 5 - 3: reserved. bit 2: enkbc = 0 kbc is disabled after hardware reset. = 1 kbc is enabled after hardware reset. this bit is read only, and set/reset by power-on setting pin. the corresponding power-on setting pin is souta (pin 54).
137 bit 1: reserved bit 0: pnpcsv = 0 the compatible pnp address select registers have default values. = 1 the compatible pnp address select registers have no default value. when trying to make a change to this bit, new value of pnpcvs must be complementary to the old one to make an effective change. for example, the user must set pnpcvs to 0 first and then reset it to 1 to reset these pnp registers if the present value of pnpcvs is 1. the corresponding power-on setting pin is ndtra (pin 52). cr25 (default 0x00) bit 7 - 6: reserved bit 5: urbtri bit 4: uratri bit 3: prttri bit 2 - 1: reserved bit 0: fdctri cr26 (default 0b0s000000) bit 7: sel4fdd = 0 select two fdd mode. = 1 select four fdd mode. bit 6: hefras these two bits define how to enable configuration mode. the corresponding power-on setting pin is nrtsa (pin 51). hefras address and value = 0 write 87h to the location 2e twice. = 1 write 87h to the location 4etwice. bit 5: lockreg = 0 enable r/w configuration registers. = 1 disable r/w configuration registers. bit 4:reserve bit 3: dsfdlgrq = 0 enable fdc legacy mode on irq and drq selection, then do register bit 3 is effective on selecting irq = 1 disable fdc legacy mode on irq and drq selection, then do register bit 3 is not effective on selecting irq bit 2: dsprlgrq = 0 enable prt legacy mode on irq and drq selection, then dcr bit 4 is effective on selecting irq = 1 disable prt legacy mode on irq and drq selection, then dcr bit 4 is not effective on selecting irq bit 1: dsualgrq = 0 enable uart a legacy mode irq selecting, then mcr bit 3 is effective on selecting irq = 1 disable uart a legacy mode irq selecting, then mcr bit 3 is not effective on selecting irq bit 0: dsublgrq = 0 enable uart b legacy mode irq selecting, then mcr bit 3 is effective on selecting irq
138 = 1 disable uart b legacy mode irq selecting, then mcr bit 3 is not effective on selecting irq cr28 (default 0x00) bit 7 - 3: reserved. bit 2 - 0: prtmods2 - prtmods0 = 0xx parallel port mode = 100 reserved = 101 external fdc mode = 110 reserved = 111 external two fdc mode cr29 (gpio3 multiplexed pin selection register. vbat powered. default 0x00) bit 7: pin64s = 0 susled (susled control bits are in crf3 of logical device 9) = 1 gp35 bit 6: pin69s = 00 ncirrx = 01 gp34 bit 5: pin70s = 0 nrsmrst = 1 gp33 bit 4: pin71s = 0 pwrok = 1 gp32 bit 3: pin72s = 0 npwrctl = 1 gp31 bit 2: pin 73s = 0 nslp_sx = 1 gp30 bit 1: reserved bit 0: reserved
139 cr2a (gpio multiplexed pin selection register 1. vcc powered. default 0x7c) bit 7: port select (select game port or general purpose i/o port 1) = 0 game port = 1 general purpose i/o port 1 (pin121~128 select function gp10~gp17 or kbc port 1) bit 6: pin128s = 0 8042 p12 = 1 gp10 bit 5: pin127s = 0 8042 p13 = 1 gp11 bit 4: pin126s = 0 8042 p14 = 1 gp12 bit 3: pin125s = 0 8042 p15 = 1 gp13 bit 2: pin124s = 0 8042 p16 = 1 gp14 bit 1: pin120s = 0 mso (midi serial output) = 1 irqin0 (select irq resource through crf4 bit 7-4 of logical device 8) bit 1: pin1119s = 0 ms1 (midi serial input) = 1 gp20 cr2b (gpio multiplexed pin selection register 2. vcc powered. default 0xc0) bit 7:pin91s = 0 scl = 1 gp21 bit 6:pin90s = 0 sda = 1 gp22 bit 5: pin89s = 0 pled (pled0 control bits are in crf5 of logical device 8) = 1 gp23 bit 4: pin88s = 0 wdto (watch dog timer is controlled by crf5, crf6, crf7 of logical device 8) = 1 gp24 bit 3: pin87s = 0 irrx = 1 gp25 bit 2: pin86s = 0 irtx = 1 gp26
140 bit 1-0:pin 2s = 00 drvden1 = 01 irqin1 (select irq resource through crf4 bit 7-4 of logical device8) = 10 reserved = 11 gp27 cr2c (default 0x00) reserved cr2e (default 0x00) test modes: reserved for smsc. cr2f (default 0x00) test modes: reserved for smsc. logical device 0 (fdc) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0xf0 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select fdc i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x06 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit 3 - 0: these bits select irq resource for fdc. cr74 (default 0x02 if pnpcsv = 0 during por, default 0x04 otherwise) bit 7 - 3: reserved. bit 2 - 0: these bits select drq resource for fdc. = 0x00 dma0 = 0x01 dma1 = 0x02 dma2 = 0x03 dma3 = 0x04 - 0x07 no dma active crf0 (default 0x0e) fdd mode register bit 7: fipurdwn this bit controls the internal pull-up resistors of the fdc input pins rdata, index, trak0, dskchg, and wp. = 0 the internal pull-up resistors of fdc are turned on.(default) = 1 the internal pull-up resistors of fdc are turned off. bit 6: intvertz this bit determines the polarity of all fdd interface signals. = 0 fdd interface signals are active low. = 1 fdd interface signals are active high. bit 5: drv2en (ps2 mode only) when this bit is a logic 0, indicates a second drive is installed and is reflected in status register a.
141 bit 4: swap drive 0, 1 mode = 0 no swap (default) = 1 drive and motor sel 0 and 1 are swapped. bit 3 - 2 interface mode = 11 at mode (default) = 10 (reserved) = 01 ps/2 = 00 model 30 bit 1: fdc dma mode = 0 burst mode is enabled = 1 non-burst mode (default) bit 0: floppy mode = 0 normal floppy mode (default) = 1 enhanced 3-mode fdd crf1 (default 0x00) bit 7 - 6: boot floppy = 00 fdd a = 01 fdd b = 10 fdd c = 11 fdd d bit 5, 4: media id1, media id0. these bits will be reflected on fdc's tape drive register bit 7, 6. bit 3 - 2: density select = 00 normal (default) = 01 normal = 10 1 (forced to logic 1) = 11 0 (forced to logic 0) bit 1: disfddwr = 0 enable fdd write. = 1 disable fdd write (forces pins we, wd stay high). bit 0: swwp = 0 normal, use wp to determine whether the fdd is write protected or not. = 1 fdd is always write-protected. crf2 (default 0xff) bit 7 - 6: fdd d drive type bit 5 - 4: fdd c drive type bit 3 - 2: fdd b drive type bit 1 - 0: fdd a drive type crf4 (default 0x00) fdd0 selection: bit 7: reserved. bit 6: precomp. disable. = 1 disable fdc precompensation. = 0 enable fdc precompensation. bit 5: reserved. bit 4 - 3: drts1, drts0: data rate table select (refer to table a). = 00 select regular drives and 2.88 format = 01 3-mode drive = 10 2 meg tape = 11 reserved
142 bit 2: reserved. bit 1:0: dtype0, dtype1: drive type select (refer to table b). crf5 (default 0x00) fdd1 selection: same as fdd0 of crf4. table a drive rate table select data rate selected data rate selden drts1 drts0 drate1 drate0 mfm fm 1 1 1meg --- 1 0 0 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 1 1 1meg --- 1 0 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 1 1 1meg --- 1 1 0 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 table b dtype0 dtype1 drvden0 (pin 2) drvden1 (pin 3) drive type 0 0 selden drate0 4/2/1 mb 3.5?? 2/1 mb 5.25? 2/1.6/1 mb 3.5? (3-mode) 0 1 drate1 drate0 1 0 nselden drate0 1 1 drate0 drate1 logical device 1 (parallel port) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0x78 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select parallel port i/o base address. [0x100:0xffc] on 4 byte boundary (epp not supported) or [0x100:0xff8] on 8 byte boundary (all modes supported, epp is only available when the base address is on 8 byte boundary). cr70 (default 0x07 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit [3:0]: these bits select irq resource for parallel port. cr74 (default 0x04) bit 7 - 3: reserved. bit 2 - 0: these bits select drq resource for parallel port.
143 0x00=dma0 0x01=dma1 0x02=dma2 0x03=dma3 0x04 - 0x07= no dma active crf0 (default 0x3f) bit 7: reserved. bit 6 - 3: ecp fifo threshold. bit 2 - 0: parallel port mode (cr28 prtmods2 = 0) = 100 printer mode (default) = 000 standard and bi-direction (spp) mode = 001 epp - 1.9 and spp mode = 101 epp - 1.7 and spp mode = 010 ecp mode = 011 ecp and epp - 1.9 mode = 111 ecp and epp - 1.7 mode. logical device 2 (uart a)) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0xf8 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select serial port 1 i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x04 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit 3 - 0: these bits select irq resource for serial port 1. crf0 (default 0x00) bit 7 - 2: reserved. bit 1 - 0: suaclkb1, suaclkb0 = 00 uart a clock source is 1.8462 mhz (24mhz/13) = 01 uart a clock source is 2 mhz (24mhz/12) = 10 uart a clock source is 24 mhz (24mhz/1) = 11 uart a clock source is 14.769 mhz (24mhz/1.625) logical device 3 (uart b) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x02, 0xf8 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select serial port 2 i/o base address [0x100:0xff8] on 8 byte boundary.
144 cr70 (default 0x03 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit [3:0]: these bits select irq resource for serial port 2. crf0 (default 0x00) bit 7 - 4: reserved. bit 3: rxw4c = 0 no reception delay when sir is changed from tx mode to rx mode. = 1 reception delays 4 characters-time (40 bit-time) when sir is changed from tx mode to rx mode. bit 2: txw4c = 0 no transmission delay when sir is changed from rx mode to tx mode. = 1 transmission delays 4 characters-time (40 bit-time) when sir is changed from rx mode to tx mode. bit 1 - 0: subclkb1, subclkb0 = 00 uart b clock source is 1.8462 mhz (24mhz/13) = 01 uart b clock source is 2 mhz (24mhz/12) = 10 uart b clock source is 24 mhz (24mhz/1) = 11 uart b clock source is 14.769 mhz (24mhz/1.625) crf1 (default 0x00) bit 7: reserved. bit 6: irlocsel. ir i/o pins' location select. = 0 through sinb/soutb. = 1 through irrx/irtx. bit 5: irmode2. ir function mode selection bit 2. bit 4: irmode1. ir function mode selection bit 1. bit 3: irmode0. ir function mode selection bit 0. ir mode ir function irtx irrx 00x disable tri-state high 010* irda active pulse 1.6 ' s demodulation into sinb/irrx 011* irda active pulse 3/16 bit time demodulation into sinb/irrx 100 ask-ir inverting irtx/soutb pin routed to sinb/irrx 101 ask-ir inverting irtx/soutb & 500 khz clock routed to sinb/irrx 110 ask-ir inverting irtx/soutb demodulation into sinb/irrx 111* ask-ir inverting irtx/soutb & 500 khz clock demodulation into sinb/irrx note: the notation is normal mode in the ir function. bit 2: hduplx. ir half/full duplex function select. = 0 the ir function is full duplex. = 1 the ir function is half duplex. bit 1: tx2inv. = 0 the soutb pin of uart b function or irtx pin of ir function in normal condition. = 1 inverse the soutb pin of uart b function or irtx pin of ir function. bit 0: rx2inv. = 0 the sinb pin of uart b function or irrx pin of ir function in normal condition. = 1 inverse the sinb pin of uart b function or irrx pin of ir function
145 logical device 5 (kbc) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x60 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the first kbc i/o base address [0x100:0xfff] on 1 byte boundary. cr62, cr 63 (default 0x00, 0x64 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the second kbc i/o base address [0x100:0xfff] on 1 byte boundary. cr70 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit [3:0]: these bits select irq resource for kint (keyboard). cr72 (default 0x0c if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit [3:0]: these bits select irq resource for mint (ps2 mouse) crf0 (default 0x80) bit 7 - 6: kbc clock rate selection = 00 select 6mhz as kbc clock input. = 01 select 8mhz as kbc clock input. = 10 select 12mhz as kbc clock input. = 11 select 16mhz as kbc clock input. bit 5 - 3: reserved. bit 2: = 0 port 92 disable. = 1 port 92 enable. bit 1: = 0 gate20 software control. = 1 gate20 hardware speed up. bit 0: = 0 kbrst software control. = 1 kbrst hardware speed up. logical device 6 (cir) cr30 (default 0x00) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x00) these two registers select cir i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x00) bit 7 - 4: reserved. bit [3:0]: these bits select irq resource for cir.
146 logical device 7 (game port and midi port and gpio port 1) cr30 (default 0x00) bit 7 - 1: reserved. bit 0: = 1 activate game port and midi port. = 0 game port and midi port is inactive. cr60, cr 61 (default 0x02, 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the game port base address [0x100:0xfff] on 1 byte boundary. cr62, cr 63 (default 0x03, 0x30 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the midi port base address [0x100:0xfff] on 2 byte boundary. cr70 (default 0x09 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4: reserved. bit [3:0]: these bits select irq resource for midi port . crf0 (gp10-gp17 i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp10-gp17 data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp10-gp17 inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. logical device 8 (gpio port 2) cr30 (gp20-gp27 default 0x00) bit 7 - 1: reserved. bit 0: = 1 activate gpio2. = 0 gpio2 is inactive. crf0 (gp20-gp27 i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp20-gp27 data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp20-gp27 inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf3 (default 0x00) bit 7 - 4: these bits select irq resource for irqin1. bit 3 - 0: these bits select irq resource for irqin0. crf4 (reserved) crf5 (pled mode register. default 0x00) bit 7-6: select pled mode = 00 power led pin is tri-stated. = 01 power led pin is drived low. = 10 power led pin is a 1hz toggle pulse with 50 duty cycle. = 11 power led pin is a 1/4hz toggle pulse with 50 duty cycle. bit 5-4: reserved bit 3: select wdto count mode.
147 = 0 second = 1 minute bit 2: enable the rising edge of keyboard reset (p20) to force time-out event. = 0 disable = 1 enable bit 1-0: reserved crf6 (default 0x00) watch dog timer time-out value. writing a non-zero value to this register causes the counter to load the value to watch dog counter and start counting down. if the bit 7 and bit 6 are set, any mouse interrupt or keyboard interrupt event will also cause the reload of previously-loaded non-zero value to watch dog counter and start counting down. reading this register returns current value in watch dog counter instead of watch dog timer time-out value. bit 7 - 0: = 0x00 time-out disable = 0x01 time-out occurs after 1 second/minute = 0x02 time-out occurs after 2 second/minutes = 0x03 time-out occurs after 3 second/minutes ................................................ = 0xff time-out occurs after 255 second/minutes crf7 (default 0x00) bit 7: mouse interrupt reset enable or disable = 1 watch dog timer is reset upon a mouse interrupt = 0 watch dog timer is not affected by mouse interrupt bit 6: keyboard interrupt reset enable or disable = 1 watch dog timer is reset upon a keyboard interrupt = 0 watch dog timer is not affected by keyboard interrupt bit 5: force watch dog timer time-out, write only* = 1 force watch dog timer time-out event; this bit is self-clearing. bit 4: watch dog timer status, r/w = 1 watch dog timer time-out occurred. = 0 watch dog timer counting bit 3 -0: these bits select irq resource for watch dog. setting of 2 selects smi. logical device 9 (gpio port 3 this power of the port is standby source (vsb) ) cr30 (default 0x00) bit 7 - 1: reserved. bit 0: = 1 activate gpio3. = 0 gpio3 is inactive. crf0 (gp30-gp35 i/o selection register. default 0xff bit 7-6: reserve) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp30-gp35 data register. default 0x00 bit 7-6: reserve) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, then its respective bit can only be read. crf2 (gp30-gp35 inversion register. default 0x00 bit 7-6: reserve) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf3 (susled mode register. default 0x00) bit 7-6: select suspend led mode
148 = 00 suspend led pin is drived low. = 01 suspend led pin is tri-stated. = 10 suspend led pin is a 1hz toggle pulse with 50 duty cycle. = 11 suspend led pin is a 1/4hz toggle pulse with 50 duty cycle. this mode selection bit 7-6 keep its settings until battery power loss. bit 5 - 0: reserved. logical device a (acpi) cr30 (default 0x00) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr70 (default 0x00) bit 7 - 4: reserved. bit 3 - 0: these bits select irq resources for npme. cre0 (default 0x00) bit 7: dis-pansw_in. disable panel switch input to turn system power supply on. = 0 pansw_in is wire-anded and connected to pansw_out. = 1 pansw_in is blocked and can not affect pansw_out. bit 6: enkbwakeup. enable keyboard to wake-up system via pansw_out. = 0 disable keyboard wake-up function. = 1 enable keyboard wake-up function. bit 5: enmswakeup. enable mouse to wake-up system via pansw_out. = 0 disable mouse wake-up function. = 1 enable mouse wake-up function. bit 4: msrkey. select mouse left/right botton to wake-up system via pansw_out. = 0 select click on mouse left-botton twice to wake the system up. = 1 select click on mouse right-botton twice to wake the system up. bit 3: encirwakeup. enable cir to wake-up system via pansw_out. = 0 disable cir wake-up function. = 1 enable cir wake-up function. bit 2: kb/ms swap. enable keyboard/mouse port-swap. = 0 keyboard/mouse ports are not swapped. = 1 keyboard/mouse ports are swapped. bit 1: msxkey. enable any character received from mouse to wake-up the system. = 0 only click mouse left/right-botton twice can wake the system up. = 1 only click mouse left/right-botton once can wake the system up. bit 0: kbxkey. enable any character received from keyboard to wake-up the system. = 0 only predetermined specific key combination can wake up the system. = 1 any character received from keyboard can wake up the system. cre1 (default 0x00) keyboard wake-up index register this register is used to indicate which keyboard wake-up shift register or predetermined key register is to be read/written via cre2. the range of keyboard wake-up index register is 0x00 - 0x19, and the range of cir wake-up index register is 0x20 - 0x2f. cre2 keyboard wake-up data register this register holds the value of wake-up key register indicated by cre1. this register can be read/written. cre3 (read only) keyboard/mouse wake-up status register bit 7-5: reserved.
149 bit 4: pwrloss_sts: this bit is set when power loss occurs. bit 3: cir_sts. the panel switch event is caused by cir wake-up event. this bit is cleared by reading this register. bit 2: pansw_sts. the panel switch event is caused by pansw_in. this bit is cleared by reading this register. bit 1: mouse_sts. the panel switch event is caused by mouse wake-up event. this bit is cleared by reading this register. bit 0: keyboard_sts. the panel switch event is caused by keyboard wake-up event. this bit is cleared by reading this register. cre4 (default 0x00) bit 7: power loss control bit 2. 0 = disable acpi resume. 1 = enable acpi resume. bit 6-5: power loss control bit <1:0> 00 = system always turn off when come back from power loss state. 01 = system always turn on when come back from power loss state. 10 = system turn on/off when come back from power loss state depend on the state before power loss. 11 = reserved. bit 4: suspend clock source select 0 = use internal clock source. 1 = use external suspend clock source(32.768khz). bit 3: keyboard wake-up type select for wake-up the system from s1/s2. 0 = password or hot keys programmed in the registers. 1 =any key. bit 2: enable all wake-up event set in cre0 can wake-up the system from s1/s2 state. this bit is cleared when wake-up event occurs. 0 = disable. 1 = enable. bit 1 - 0: reserved. cre5 (default 0x00) bit 7: reserved. bit 6 - 0: compared code length. when the compared codes are storaged in the data register, these data length should be written to this register. cre6 (default 0x00) bit 7 - 6: reserved. bit 5 - 0: cir baud rate divisor. the clock base of cir is 32khz, so that the baud rate is 32khz divided by ( cir baud rate divisor + 1).
150 cre7 (default 0x00) bit 7 - 3: reserved. bit 2: reset cir power-on function. after using cir power-on, the software should write logical 1 to restart cir power-on function. bit 1: invert rx data. = 1 inverting rx data. = 0 not inverting rx data. bit 0: enable demodulation. = 1 enable received signal to demodulate. = 0 disable received signal to demodulate. crf0 (default 0x00) bit 7: chippme. chip level auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 6: cirpme. consumer ir port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 5: midipme. midi port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 4: reserved. return zero when read. bit 3: prtpme. printer port auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 2: fdcpme. fdc auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 1: urapme. uart a auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 0: urbpme. uart b auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. crf1 (default 0x00) bit 7: wak_sts. this bit is set when the chip is in the sleeping state and an enabled resume event occurs. upon setting this bit, the sleeping/working state machine will transition the system to the working state. this bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. = 0 the chip is in the sleeping state. = 1 the chip is in the working state. bit 6 - 5: devices' trap status. bit 4: reserved. return zero when read. bit 3 - 0: devices' trap status.
151 crf3 (default 0x00) bit 7 - 6: reserved. return zero when read. bit 5 - 0: device's irq status. these bits indicate the irq status of the individual device respectively. the device's irq status bit is set by their source device and is cleared by writing a 1. writing a 0 has no effect. bit 5: mouirqsts. mouse irq status. bit 4: kbcirqsts. kbc irq status. bit 3: prtirqsts. printer port irq status. bit 2: fdcirqsts. fdc irq status. bit 1: urairqsts. uart a irq status. bit 0: urbirqsts. uart b irq status. crf4 (default 0x00) bit 7 - 6: reserved. return zero when read. bit 5 - 0: these bits indicate the irq status of the individual gpio function or logical device respectively. the status bit is set by their source function or device and is cleared by writing a 1. writing a 0 has no effect. bit 5: hmirqsts. hardware monitor irq status. bit 4: wdtirqsts. watch dog timer irq status. bit 3: cirirqsts. consumer ir irq status. bit 2: midiirqsts. midi irq status. bit 1: irqin1sts. irqin1 status. bit 0: irqin0sts. irqin0 status. crf6 (default 0x00) bit 7 - 6: reserved. return zero when read. bit 5 - 0: enable bits of the nsmi/npme generation due to the device's irq. these bits enable the generation of an nsmi/npme interrupt due to any irq of the devices. nsmi/npme logic output = (mouirqen and mouirqsts) or (kbcirqen and kbcirqsts) or (prtirqen and prtirqsts) or (fdcirqen and fdcirqsts) or (urairqen and urairqsts) or (urbirqen and urbirqsts) or (hmirqen and hmirqsts) or (wdtirqen and wdtirqsts) or (irqin3en and irqin3sts) or (irqin2en and irqin2sts) or (irqin1en and irqin1sts) or (irqin0en and irqin0sts) bit 5: mouirqen. = 0 disable the generation of an nsmi/npme interrupt due to mouse's irq. = 1 enable the generation of an nsmi/npme interrupt due to mouse's irq. bit 4: kbcirqen. = 0 disable the generation of an nsmi/npme interrupt due to kbc's irq. = 1 enable the generation of an nsmi/npme interrupt due to kbc's irq. bit 3: prtirqen. = 0 disable the generation of an nsmi/npme interrupt due to printer port's irq. = 1 enable the generation of an nsmi/npme interrupt due to printer port's irq. bit 2: fdcirqen. = 0 disable the generation of an nsmi/npme interrupt due to fdc's irq. = 1 enable the generation of an nsmi/npme interrupt due to fdc's irq. bit 1: urairqen. = 0 disable the generation of an nsmi/npme interrupt due to uart a's irq. = 1 enable the generation of an nsmi/npme interrupt due to uart a's irq. bit 0: urbirqen. = 0 disable the generation of an nsmi/npme interrupt due to uart b's irq.
152 = 1 enable the generation of an nsmi/npme interrupt due to uart b's irq. crf7 (default 0x00) bit 7 - 6: reserved. return zero when read. bit 5 - 0: enable bits of the generation due to the gpio irq function or device's irq. bit 5: hmirqen. = 0 disable the generation of an nsmi/npme interrupt due to hardware monitor's irq. = 1 enable the generation of an nsmi/npme interrupt due to hardware monitor's irq. bit 4: wdtirqen. = 0 disable the generation of an nsmi/npme interrupt due to watch dog timer's irq. = 1 enable the generation of an nsmi/npme interrupt due to watch dog timer's irq. bit 3: cirirqen. = 0 disable the generation of an nsmi/npme interrupt due to cir's irq. = 1 enable the generation of an nsmi/npme interrupt due to cir's irq. bit 2: midiirqen. = 0 disable the generation of an nsmi/npme interrupt due to midi's irq. = 1 enable the generation of an nsmi/npme interrupt due to midi's irq. bit 1: irqin1en. = 0 disable the generation of an nsmi/npme interrupt due to irqin1's irq. = 1 enable the generation of an nsmi/npme interrupt due to irqin1's irq. bit 0: irqin0en. = 0 disable the generation of an nsmi/npme interrupt due to irqin0's irq. = 1 enable the generation of an nsmi/npme interrupt due to irqin0's irq. crf9 (default 0x00) bit 7 - 3: reserved. return zero when read. bit 2: pme_en: select the power management events to be either an npme or nsmi interrupt for the irq events. note that: this bit is valid only when smipme_oe = 1. = 0 the power management events will generate an nsmi event. = 1 the power management events will generate an npme event. bit 1: fsleep: this bit selects the fast expiry time of individual devices. = 0 1 second. = 1 8 milli-seconds. bit 0: smipme_oe: this is the nsmi and npme output enable bit. = 0 neither nsmi nor npme will be generated. only the irq status bit is set. = 1 an nsmi or npme event will be generated. crfe, ff (default 0x00) reserved for smsc test.
153 logical device b (hardware monitor) cr30 (default 0x00) bit 7 - 1: reserved. bit 0: = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x00) these two registers select hardware monitor base address [0x100:0xfff] on 8-byte boundary. cr70 (default 0x00) bit 7 - 4: reserved. bit 3 - 0: these bits select irq resource for hardware monitor. crf0 (default 0x00) bit 7 - 1: reserved. bit 0: disable initial abnormal beep (vcorea and +3.3 v) = 0 enable power-on abnormal beep = 1 disable power-on abnormal beep
154 specifications absolute maximum ratings parameter rating unit power supply voltage (5v) -0.5 to 7.0 v input voltage -0.5 to vdd+0.5 v rtc battery voltage vbat 1.8 to 4.0 v operating temperature 0 to +70 / c storage temperature -55 to +150 / c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (ta = 0 / c to 70 / c, vdd = 5v 1 10%, vss = 0v) parameter sym. min. typ. max. unit conditions rtc battery quiescent current ibat 2.4 ua vbat = 2.5 v acpi stand-by power supply quiescent current ibat 2.0 ma vsb = 5.0 v, all acpi pins are not connected. i/o 8t - ttl level bi-directional pin with source-sink capability of 8 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 8 ma output high voltage voh 2.4 v ioh = - 8 ma input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0v i/o 12t - ttl level bi-directional pin with source-sink capability of 12 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = -12 ma input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0v
155 dc characteristics, continued parameter sym. min. typ. max. unit conditions i/o 12tp3 - 3.3 v ttl level bi-directional pin with source-sink capability of 12 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = -12 ma input high leakage ilih +10 ' a vin = 3.3v input low leakage ilil -10 ' a vin = 0v i/od 12t - ttl level bi-directional pin with sink capability of 12 ma and open-drain input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 12 ma input high leakage ilih +10 ' a vin = 3.3v input low leakage ilil -10 ' a vin = 0v i/o 24t - ttl level bi-directional pin with source-sink capability of 24 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 24 ma output high voltage voh 2.4 v ioh = -24 ma input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0v out 12t - ttl level output pin with source-sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = -12 ma out 12tp3 - 3.3 v ttl level output pin with source-sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = -12 ma od 12 - open-drain output pin with sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma od 24 - open-drain output pin with sink capability of 24 ma output low voltage vol 0.4 v iol = 24 ma
156 dc characteristics, continued parameter sym. min. typ. max. unit conditions in td - ttl level input pin with internal pull down resistor input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0 v pull down resistor r 47 k " in t - ttl level input pin input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0 v in cs - cmos level schmitt-triggered input pin input low threshold voltage vt- 1.3 1.5 1.7 v vdd = 5 v input high threshold voltage vt+ 3.2 3.5 3.8 v vdd = 5 v hystersis vth 1.5 2 v vdd = 5 v input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0 v in ts - ttl level schmitt-triggered input pin input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 5 v input high threshold voltage vt+ 1.6 2.0 2.4 v vdd = 5 v hystersis vth 0.5 1.2 v vdd = 5 v input high leakage ilih +10 ' a vin = vdd input low leakage ilil -10 ' a vin = 0 v in tsp3 - 3.3 v ttl level schmitt-triggered input pin input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 3.3 v input high threshold voltage vt+ 1.6 2.0 2.4 v vdd = 3.3 v hystersis vth 0.5 1.2 v vdd = 3.3 v input high leakage ilih +10 ' a vin = 3.3 v input low leakage ilil -10 ' a vin = 0 v
157 application circuits parallel port extension fdd printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 nwe2/slct nwd2/pe nmob2/busy ndsb2/ack pd7 pd6 pd5 ndch2/pd4 rdd2/pd3 nstep2/nslin nwp2/pd2 ndir2/ninit ntrk02/pd1 nhead2/nerr nidx2/pd0 nrwc2/nafd nstb 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 jp 13a ext fdc ndch2 ntrk02 nrdd2 ndir2 nwp2 nmob2 nrwc2 ndsb2 nhead2 nstep2 nwd2 nwe2 nidx2 parallel port extension fdd mode connection diagram
158 parallel port extension 2fdd four fdd mode 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 nwe2/slct nwd2/pe nmob2/busy ndsb2/ack pd5 ndch2/pd4 nrdd2/pd3 nstep2/nslin nwp2/pd2 ndir2/ninit ntrk02/pd1 nhead2/nerr nidx2/pd0 nrwc2/nafd nstb jp 13a ext fdc ndch2 ntrk02 nrdd2 ndir2 nwp2 nmob2 nrwc2 ndsb2 nhead2 nstep2 nwd2 nwe2 nidx2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 ndsa2 nmoa2 parallel port extension 2fdd connection dia g ram ndsa2/pd7 nmoa2/pd6 g1 a1 b1 g2 a2 b2 1y0 1y1 1y2 1y3 2y0 2y1 2y2 2y3 ndsa ndsb nmoa nmob fdc97w352/362 74ls139 7407(2) ndsa nmoa nmod nmoc nmob ndsc ndsd ndsb
159 package dimensions (128 pin qfp) l l 1 detail f c e b 1 38 h d d 39 64 h e e 102 65 1.dimension d & e do not include interlead flash. 2.dimension b does not include dambar protrusion/intrusion 3.controlling dimension : millimeter 4.general appearance spec. should be based on final visual inspection spec. . note: seating plane see detail f y a a 1 a 2 128 103 5. pcb layout please use the "mm". symbol b c d e h d h e l y 0 a a l 1 1 2 e 7 0 0.08 1.60 0.95 17.40 0.80 17.20 0.65 17.00 14.10 0.20 0.30 2.87 14.00 2.72 0.50 13.90 0.10 0.10 2.57 0.25 min nom max dimension in mm 0.20 0.15 19.90 20.00 20.10 23.00 23.20 23.40 0.35 0.45 0.003 0 0.063 0.037 0.685 0.031 0.677 0.025 0.669 0.020 0.555 0.008 0.012 0.113 0.551 0.107 0.547 0.004 0.004 0.101 0.010 max nom min dimension in inch 0.006 0.008 7 0.783 0.787 0.791 0.905 0.913 0.921 0.014 0.018
160 ? standard microsystems corporation (smsc) 2000 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 standard microsystems is a registered trademark of standard microsystems corporation, and smsc is a trademark of standard microsystems corporation. pentium is a registered trademark of intel corporation. product names and company names are the trademarks of their respective holders. circuit diagrams utilizing smsc products are included as a means of illustrating typic al applications; consequently complete information sufficient for construction purposes is not necessarily given. although the in formation has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to mak e changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain t he latest specifications before placing your product order. the provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated befor e the date of your order (the "terms of sale agreement"). the product may contain design defects or errors known as anomalies wh ich may cause the product's functions to deviate from published specifications. anomaly sheets are available upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product fai lure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an o fficer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http:// www.smsc.com. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, punitive, or consequential damages, or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract, tort, negligence of smsc or others, strict liability, breach of warranty, or otherwise; whether or not any remedy is held to have failed of its essential purpose; and whether or not smsc has been advised of the possibility of such damages. LPC61W492 rev. 03/29/2000

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